BQ24765_15 Datasheet, PDF (22/43 Pages) Texas Instruments – SMBus-Controlled Multi-Chemistry Battery Charger With Integrated Power MOSFETs

bq24765
SLUS999A – NOVEMBER 2009 – REVISED NOVEMBER 2015
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8.5.1.1 SMBus Interface
The bq24765 operates as a slave, receiving control inputs from the embedded controller host through the SMBus
interface.
The bq24765 receives control inputs from the SMBus interface. The bq24765 uses a simplified subset of the
commands documented in System Management Bus Specification V1.1, which can be downloaded from
www.smbus.org. The bq24765 uses the SMBus Read-Word and Write-Word protocols (see Figure 14) to
communicate with the smart battery. The bq24765 performs only as an SMBus slave device with address
0b0001001_ (0x12) and does not initiate communication on the bus. In addition, the bq24765 has two
identification (ID) registers (0xFE): a 16-bit device ID register and a 16-bit manufacturer ID register (0xFF).
The data (SDA) and clock (SCL) pins have Schmitt-trigger inputs that can accommodate slow edges. Choose
pullup resistors (10 kΩ) for SDA and SCL to achieve rise times according to the SMBus specifications.
Communication starts when the master signals a START condition, which is a high-to-low transition on SDA,
while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a
low-to-high transition on SDA, while SCL is high. The bus is then free for another transmission. Figure 15 and
Figure 16 show the timing diagram for signals on the SMBus interface. The address byte, command byte, and
data bytes are transmitted between the START and STOP conditions. The SDA state changes only while SCL is
low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising
edge of SCL. Nine clock cycles are required to transfer each byte in or out of the bq24765 because either the
master or the slave acknowledges the receipt of the correct byte during the ninth clock cycle.
a) Write-Word Format
S
SLAVE
ADDRESS
W
ACK
COMMAND
BYTE
ACK
LOW DATA
BYTE
7 BITS
1b 1b
8 BITS
1b 8 BITS
MSB LSB 0
0
MSB LSB
0 MSB LSB
Preset to 0b0001001
ChargerMode() = 0x12 D7 D0
ChargeCurrent() = 0x14
ChargeVoltage() = 0x15
InputCurrent() = 0x3F
ACK
1b
0
HIGH DATA
BYTE
8 BITS
MSB L SB
D15 D8
ACK P
1b
0
b) Read-Word Format
S
SLAVE
ADDRESS
W
ACK
COMMAND
BYTE
ACK S
SLAVE
ADDRESS
R
ACK
LOW DATA
BYTE
ACK
HIGH DATA
BYTE
NACK P
7 BITS 1b 1b
8 BITS
1b
7 BITS
1b 1b
8 BITS
1b
8 BITS
1b
MSB LSB 0 0
MSB LSB
0
MSB LSB 1
0 MSB LSB 0 MSB LSB
1
Preset to 0b0001001
Register
ChargerMode() = 0x12
ChargeMode() = 0x14
ChargeMode() = 0x15
ChargeMode() = 0x3F
Preset to
0b0001001
D7 D0
D15 D8
LEGEND:
S = START CONDITION OR REPEATED START CONDITION
ACK = ACKNOWLEDGE (LOGIC-LOW)
W = WRITE BIT (LOGIC-LOW)
P = STOP CONDITION
NACK = NOT ACKNOWLEDGE (LOGIC-HIGH)
R = READ BIT (LOGIC-HIGH)
MASTER TO SLAVE
SLAVE TO MASTER
Figure 14. SMBus Write-Word and Read-Word Protocols
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