BQ24765_15 Datasheet, PDF (3/43 Pages) Texas Instruments – SMBus-Controlled Multi-Chemistry Battery Charger With Integrated Power MOSFETs

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bq24765
SLUS999A – NOVEMBER 2009 – REVISED NOVEMBER 2015
5 Description (Continued)
The bq24765 features Dynamic Power Management (DPM) and input power limiting. These features reduce
battery charge current when the input power limit is reached to avoid overloading the AC adaptor when supplying
the load and the battery charger simultaneously. A high-accuracy current sense amplifier enables accurate
measurement of input current from the AC adapter, allowing monitoring the overall system power. If the adapter
current is above the programmed low-power threshold, a signal is sent to host so that the system optimizes its
power performance according to what is available from the adapter. An integrated comparator allows monitoring
the input current through the current sense amplifier, and indicating when the input current exceeds a
programmable threshold limit. The bq24765 features a thermal regulation loop to reduce battery charge current
when the T_j limit is reached. This feature protects internal power FETs from overheating when charging with high
current.
6 Pin Configuration and Functions
RUV Package
34-Pin VQFN
Top View
34 33 32 31 30
PGND 1
DCINP ₂
DCINP 3
DCINP ⁴
CSSN 5
CSSP 6
VREF 7
29 PHASE
28 PHASE
27 PHASE
26 BOOT
25 DCINA
24 VDDP
23 ICOUT
ICREF 8
ACIN ₉
EAO ¹⁰
EAI 11
FBO 12
22 CSOP
21 CSON
20 VFB
19 AGND
18 ACOK
13 14 15 16 17
PIN
NAME
NO.
ACIN
9
ACOK
18
AGND
19
BOOT
26
CE
13
CSON
21
CSOP
22
Pin Functions
TYPE
DESCRIPTION
I
O
AGND
P
I
P
P
Adapter detected voltage set input. Program the adapter detect threshold by connecting a resistor divider from
adapter input to ACIN pin to AGND pin. ACOK open-drain output is pulled high and charge is allowed when
ACIN pin voltage is greater than 2.4V. VREF regulator and VICM current sense amplifier are active when
ACIN pin voltage is greater than 0.6V, and DCINA>V_{DCIN_UVLO}.
Valid adapter active-high detect logic open-drain output. Pulled HI when Input voltage is above ACIN
programmed threshold and DCINA is above UVLO threshold. Connect a 10-kΩ pull-up resistor from ACOK
pin to pull-up supply rail.
Analog Ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the
power-pad underneath the IC.
PWM high side driver positive supply. Connect a 0.1uF bootstrap ceramic capacitor from BOOT to PHASE.
Connect a small bootstrap Schottky diode from VDDP to BOOT.
Charge enable active-high logic input. HI enables charge. LO disables charge. Pull up CE using 10kOhm
resistor or connect directly to VREF to enable charger.
Charge current sense resistor, negative input. An optional 0.1-uF ceramic capacitor is placed from CSON pin
to AGND for common-mode filtering. A 0.1-uF ceramic capacitor is placed from CSON to CSOP to provide
differential-mode filtering. The capacitor of the output LC filter is placed on CSON.
Charge current sense resistor, positive input. A 0.1-uF ceramic capacitor is placed from CSOP pin to AGND
for common mode filtering. A 0.1-uF ceramic capacitor is placed from CSON to CSOP to provide differential-
mode filtering.
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