MSP430F249-EP_14 Datasheet, PDF (48/82 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F249-EP
MIXED SIGNAL MICROCONTROLLER
2008
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
USCI (UART mode)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX UNIT
f_USCI
USCI input clock frequency
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
f_SYSTEM MHz
f_BITCLK
BITCLK clock frequency
(equals Baudrate in MBaud)
2.2 V/3 V
1 MHz
UART receive deglitch time
t_τ
(see Note 1)
2.2 V
3V
50 150 600
ns
50 100 600
NOTE 1: Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are
correctly recognized their width should exceed the maximum specification of the deglitch time.
USCI (SPI master mode) (see Figure 27 and Figure 28)
PARAMETER
TEST CONDITIONS
VCC
MIN
f_USCI
USCI input clock frequency
SMCLK, ACLK
Duty cycle = 50% ± 10%
t_SU,MI
SOMI input data setup time
2.2 V
110
3V
75
t_HD,MI
SOMI input data hold time
2.2 V
3V
t_VALID,MO
SIMO output data valid time
UCLK edge to SIMO valid;
C_L = 20 pF
2.2 V
3V
NOTE:
f_UCxCLK
+
1
2t_LOńHI
with
t_LOńHI
w
max(t_{VALID,MO(USCI)}
)
t_{SU,SI(Slave),}
t_SU,MI(USCI)
)
t _{VALID,SO(Slave)}) .
For the slave’s parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, see the SPI parameters of the attached slave.
MAX UNIT
f_SYSTEM MHz
ns
ns
30
ns
20
USCI (SPI slave mode) (see Figure 29 and Figure 30)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP
t_STE,LEAD
STE lead time
STE low to clock
2.2 V/3 V
50
t_STE,LAG
STE lag time
Last clock to STE high
2.2 V/3 V
10
t_STE,ACC
STE access time
STE low to SOMI data out
2.2 V/3 V
50
t_STE,DIS
STE disable time
STE high to SOMI high impedance
2.2 V/3 V
50
t_SU,SI
SIMO input data setup time
2.2 V
20
3V
15
t_HD,SI
SIMO input data hold time
2.2 V
10
3V
10
UCLK edge to SOMI valid;
2.2 V
75
t_VALID,SO
SOMI output data valid time
C_L = 20 pF
3V
50
NOTE:
f_UCxCLK
+
1
2t_LOńHI
with
t_LOńHI
w
max(t_{VALID,MO(Master)}
)
t_SU,SI(USCI),
t_{SU,MI(Master)}
)
t_{VALID,SO(USCI)}).
For the master’s parameters t_{SU,MI(Master)} and t_{VALID,MO(Master)} refer to the SPI parameters of the attached master.
MAX UNIT
ns
ns
ns
ns
ns
ns
110
ns
75
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