LM3S2939 Datasheet, PDF (475/749 Pages) Texas Instruments – Stellaris® LM3S2939 Microcontroller

Stellaris^® LM3S2939 Microcontroller
default to be GPIO signals at reset., with the exception of the SSI0Clk, SSI0Fss, SSI0Rx, and
SSI0Tx pins which default to the SSI function. The column in the table below titled "Pin Assignment"
lists the possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate
Function Select (GPIOAFSEL) register (page 309) should be set to choose the SSI function. For
more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 285.
Table 13-1. SSI Signals (100LQFP)
Pin Name
Pin Number Pin Type Buffer Type^a Description
SSI0Clk
28
I/O
TTL
SSI module 0 clock
SSI0Fss
29
I/O
TTL
SSI module 0 frame signal
SSI0Rx
30
I
TTL
SSI module 0 receive
SSI0Tx
31
O
TTL
SSI module 0 transmit
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
Table 13-2. SSI Signals (108BGA)
Pin Name
Pin Number Pin Type Buffer Type^a Description
SSI0Clk
M4
I/O
TTL
SSI module 0 clock
SSI0Fss
L4
I/O
TTL
SSI module 0 frame signal
SSI0Rx
L5
I
TTL
SSI module 0 receive
SSI0Tx
M5
O
TTL
SSI module 0 transmit
a. The TTL designation indicates the pin has TTL-compatible voltage levels.
13.3
Functional Description
The SSI performs serial-to-parallel conversion on data received from a peripheral device. The CPU
accesses data, control, and status information. The transmit and receive paths are buffered with
internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit
and receive modes.
13.3.1
Bit Rate Generation
The SSI includes a programmable bit rate clock divider and prescaler to generate the serial output
clock. Bit rates are supported to 2 MHz and higher, although maximum bit rate is determined by
peripheral devices.
The serial bit rate is derived by dividing down the input clock (FSysClk). The clock is first divided
by an even prescale value CPSDVSR from 2 to 254, which is programmed in the SSI Clock Prescale
(SSICPSR) register (see page 494). The clock is further divided by a value from 1 to 256, which is
1 + SCR, where SCR is the value programmed in the SSI Control0 (SSICR0) register (see page 487).
The frequency of the output clock SSIClk is defined by:
SSIClk = FSysClk / (CPSDVSR * (1 + SCR))
Note: For master mode, the system clock must be at least two times faster than the SSIClk. For
slave mode, the system clock must be at least 12 times faster than the SSIClk.
See “Synchronous Serial Interface (SSI)” on page 707 to view SSI timing parameters.
June 18, 2012
475
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