LM3S2939 Datasheet, PDF (12/749 Pages) Texas Instruments – Stellaris® LM3S2939 Microcontroller

Table of Contents
Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ........ 481
Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ......................................... 482
Figure 13-10. MICROWIRE Frame Format (Single Frame) ........................................................ 482
Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ............................................. 483
Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ............ 484
Figure 14-1. I²C Block Diagram ............................................................................................. 513
Figure 14-2. I²C Bus Configuration ........................................................................................ 514
Figure 14-3. START and STOP Conditions ............................................................................. 514
Figure 14-4. Complete Data Transfer with a 7-Bit Address ....................................................... 515
Figure 14-5. R/S Bit in First Byte ............................................................................................ 515
Figure 14-6. Data Validity During Bit Transfer on the I²C Bus ................................................... 515
Figure 14-7. Master Single SEND .......................................................................................... 519
Figure 14-8. Master Single RECEIVE ..................................................................................... 520
Figure 14-9. Master Burst SEND ........................................................................................... 521
Figure 14-10. Master Burst RECEIVE ...................................................................................... 522
Figure 14-11. Master Burst RECEIVE after Burst SEND ............................................................ 523
Figure 14-12. Master Burst SEND after Burst RECEIVE ............................................................ 524
Figure 14-13. Slave Command Sequence ................................................................................ 525
Figure 15-1. CAN Controller Block Diagram ............................................................................ 550
Figure 15-2. CAN Data/Remote Frame .................................................................................. 551
Figure 15-3. Message Objects in a FIFO Buffer ...................................................................... 560
Figure 15-4. CAN Bit Time .................................................................................................... 564
Figure 16-1. Analog Comparator Module Block Diagram ......................................................... 597
Figure 16-2. Structure of Comparator Unit .............................................................................. 598
Figure 16-3. Comparator Internal Reference Structure ............................................................ 599
Figure 17-1. PWM Unit Diagram ............................................................................................ 610
Figure 17-2. PWM Module Block Diagram .............................................................................. 611
Figure 17-3. PWM Count-Down Mode .................................................................................... 612
Figure 17-4. PWM Count-Up/Down Mode .............................................................................. 613
Figure 17-5. PWM Generation Example In Count-Up/Down Mode ........................................... 613
Figure 17-6. PWM Dead-Band Generator ............................................................................... 614
Figure 18-1. QEI Block Diagram ............................................................................................ 648
Figure 18-2. Quadrature Encoder and Velocity Predivider Operation ........................................ 650
Figure 19-1. 100-Pin LQFP Package Pin Diagram .................................................................. 665
Figure 19-2. 108-Ball BGA Package Pin Diagram (Top View) ................................................... 666
Figure 22-1. Load Conditions ................................................................................................ 699
Figure 22-2. JTAG Test Clock Input Timing ............................................................................. 702
Figure 22-3. JTAG Test Access Port (TAP) Timing .................................................................. 702
Figure 22-4. JTAG TRST Timing ............................................................................................ 702
Figure 22-5. External Reset Timing (RST) .............................................................................. 703
Figure 22-6. Power-On Reset Timing ..................................................................................... 703
Figure 22-7. Brown-Out Reset Timing .................................................................................... 704
Figure 22-8. Software Reset Timing ....................................................................................... 704
Figure 22-9. Watchdog Reset Timing ..................................................................................... 704
Figure 22-10. Hibernation Module Timing ................................................................................. 705
Figure 22-11. ADC Input Equivalency Diagram ......................................................................... 706
Figure 22-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing
Measurement .................................................................................................... 707
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June 18, 2012
Texas Instruments-Production Data