LM3S2939 Datasheet, PDF (22/749 Pages) Texas Instruments – Stellaris® LM3S2939 Microcontroller

Table of Contents
Register 2:
Register 3:
Register 4:
Register 5:
Register 6:
Register 7:
Register 8:
Register 9:
Register 10:
Register 11:
Register 12:
Register 13:
Register 14:
Register 15:
Register 16:
Register 17:
Register 18:
Register 19:
Register 20:
Register 21:
Register 22:
Register 23:
Register 24:
Register 25:
UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 443
UART Flag (UARTFR), offset 0x018 ................................................................................ 445
UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 447
UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 448
UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 449
UART Line Control (UARTLCRH), offset 0x02C ............................................................... 450
UART Control (UARTCTL), offset 0x030 ......................................................................... 452
UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 454
UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 456
UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 458
UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 459
UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 460
UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 462
UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 463
UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 464
UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 465
UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 466
UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 467
UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 468
UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 469
UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 470
UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 471
UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 472
UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 473
Synchronous Serial Interface (SSI) ............................................................................................ 474
Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 487
Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 489
Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 491
Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 492
Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 494
Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 495
Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 497
Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 498
Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 499
Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 500
Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 501
Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 502
Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 503
Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 504
Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 505
Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 506
Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 507
Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 508
Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 509
Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 510
Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 511
Inter-Integrated Circuit (I²C) Interface ........................................................................................ 512
Register 1: I²C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 528
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June 18, 2012
Texas Instruments-Production Data