THS7353_15 Datasheet, PDF (41/57 Pages) Texas Instruments – 3-Channel Low Power Video Buffer with I2C Control, Selectable Filters, External Gain Control, 2:1 Input MUX, and Selectable Input Modes

THS7353
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SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012
EXAMPLE—READING FROM THE THS7353
The read operation consists of two phases. The first phase is the address phase. In this phase, an I²C master
initiates a write operation to the THS7353 by generating a start condition (S) followed by the THS7353 I²C
address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the
THS7353, the master presents the subaddress (channel) of the register it wants to read. After the cycle is
acknowledged (A), the master terminates the cycle immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I²C master initiates a read operation to the THS7353 by
generating a start condition followed by the THS7353 I²C address (as shown below for a read operation), in MSB
first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the THS7353, the I²C master
receives one byte of data from the THS7353. After the data byte has been transferred from the THS7353 to the
master, the master generates a not acknowledge followed by a stop. Similar to the Write function, to read all
channels Steps 1 through 11 must be repeated for each and every channel desired.
THS7353 Read Phase 1:
Step 1
0
I²C Start (Master)
S
Step 2
I²C General Address (Master)
7
6
5
4
3
2
1
0
0
1
0
1
1
X
X
0
Where each X Logic state is defined by I²C-A1 and I²C-A0 pins being tied to either V_S+ or GND.
Step 3
9
I²C Acknowledge (Slave)
A
Step 4
I²C Read Channel Address (Master)
7
6
5
0
0
0
Where Addr is determined by the values shown in Table 2.
Step 5
9
I²C Acknowledge (Slave)
A
4
3
2
1
0
0
0
0
Addr
Addr
Step 6
0
I²C Start (Master)
P
Copyright © 2005–2012, Texas Instruments Incorporated
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