THS7353_15 Datasheet, PDF (28/57 Pages) Texas Instruments – 3-Channel Low Power Video Buffer with I2C Control, Selectable Filters, External Gain Control, 2:1 Input MUX, and Selectable Input Modes

THS7353
SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012
www.ti.com
OUTPUT MODES OF OPERATION – AC COUPLED
A common method of coupling the video signal to an ADC or video decoder is with the use of a 0.1-μF to 1-μF
decoupling capacitor. The low 0.8-Ω at 10-MHz output impedance of the THS7353 allows driving an ADC directly
without worrying about possible kick-back current from the ADC. Additionally, the THS7353 can be used to drive
a video line which is common when using a large capacitor. This large capacitor is typically between 220 μF and
1000 μF, although 470 μF is most common. This value of this capacitor must be this large to minimize the line tilt
(droop) and/or field tilt associated with ac coupling as described previously in this document. Since the input
impedance of an ADC or video decoder is high impedance, the coupling capacitor can be much smaller than a
line’s 150-Ω impedance.
AC coupling is done for several reasons, but the most common reason is to ensure full inter-operability voltage
levels with the receiving system. This also eliminates possible ground loops, and ensures that regardless of the
reference dc voltage used on the transmit side, the receive element (either the ADC or the video transmission
line) re-establishes the dc-reference voltage to its own requirements.
Just like the dc output mode of operation discussed previously, each output should keep the capacitive loading
below 20-pF. If the THS7353 is used to drive two video transmission lines, it is best to have each line use its own
capacitor and resistor rather than sharing these components as shown in Figure 65.This helps ensure line-to-line
dc isolation, and the potential problems as stipulated above. Using a single 1000-μF capacitor for 2-lines is
possible, but there is a chance for ground loops and interference to be created between the two receivers.
3.3 V
DAC /
Encoder
Y’
(THS8200)
HDTV
480i
576i
P’_B
480p
576p
720p
1080i
P’_R
1080p
Y’
P’_B
P’_R
R
R
R
0.1 mF
75 W
1 mF
75 W
1 mF
75 W
DC + 250 mV
1 NC
NC 20
2 CH.1 IN A CH.1 OUT 19
DC + 250 mV
3
DC + 250 mV
4
AC STC
5
AC Bias
6
AC Bias
7
CH.2 IN A
CH.3 IN A
CH.1 IN B
CH.2 IN B
CH.3 IN B
CH1.
GAIN ADJ
18
CH.2 OUT 17
CH2.
GAIN ADJ
16
CH.3 OUT 15
CH3. ₁₄
GAIN ADJ
8 ^{I 2C-A1}
I2C-SCL 13
9 ^{I 2C-A0}
I2C-SDA 12
10 ^GND
V_{S+ 11}
0.01 mF
470 mF
(See Note A)
+
Y’
Out 1
75 W
470 mF
(See Note A)
+
Y’
Out 2
2.2 pF
750 W
2.2 pF
750 W
2.2 pF
750 W
5V
75 W
470 mF
(See Note A)
+
P’ B
Out 1
75 W
470 mF
P’B
(See Note A) ^{Out 2}
+
75 W
470 mF
(See Note A)
+
P’ _R
Out 1
100 mF
2
IC
Controller
75 W
470 mF
(See Note A)
+
P’R
Out 2
75 W
75 W
75 W
75 W
75 W
75 W
75 W
External
Input
A. Due to the high frequency content of the video signal, it is recommended, but not required, to add a 0.01-μF capacitor
in parallel with these large capacitors.
Figure 65. Typical Y'P'_BP'_R System Driving 2 AC-Coupled Video Lines
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