THS7353_15 Datasheet, PDF (36/57 Pages) Texas Instruments – 3-Channel Low Power Video Buffer with I2C Control, Selectable Filters, External Gain Control, 2:1 Input MUX, and Selectable Input Modes

THS7353
SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012
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During a write cycle, the transmitting device must not drive the SDA signal line during the acknowledge cycle, so
that the receiving device may drive the SDA signal low. After each byte transfer following the address byte, the
receiving device pulls the SDA line low for one SCL clock cycle. A stop condition is initiated by the transmitting
device after the last byte is transferred. An example of a write cycle can be found in Figure 74 and Figure 75.
Note that the THS7353 does not allow multiple write transfers to occur. See example section, Writing to the
THS7353 for more information.
During a read cycle, the slave receiver acknowledges the initial address byte if it decodes the address as its
address. Following this initial acknowledge by the slave, the master device becomes a receiver and
acknowledges data bytes sent by the slave. When the master has received all of the requested data bytes from
the slave, the not acknowledge (A) condition is initiated by the master by keeping the SDA signal high just before
it asserts the stop (P) condition. This sequence terminates a read cycle as shown in Figure 76 and Figure 77.
Note that the THS7353 does not allow multiple read transfers to occur. See example section, Reading from the
THS7353 for more information.
From Receiver
S Slave Address
W A DATA A DATA A P
From Transmitter
Figure 74. I²C Write Cycle
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
Start
Condition
Acknowledge
(From Receiver)
Acknowledge
(Receiver)
Acknowledge
(Transmitter)
SDA
A6 A5
A1 A0 R/W ACK D7 D6
D1 D0 ACK
D7 D6
D1 D0 ACK
I²C Device Address and
Read/Write Bit
First Data
Byte
Other
Last Data Byte
Data Bytes
Figure 75. Multiple Byte Write Transfer
Stop
Condition
S Slave Address R A DATA A DATA A P
Transmitter
Receiver
Figure 76. I²C Read Cycle
A = No Acknowledge (SDA High)
A = Acknowledge
S = Start Condition
P = Stop Condition
W = Write
R = Read
Start
Condition
Acknowledge
(From
Receiver)
Acknowledge
(From
Transmitter)
Not
Acknowledge
(Transmitter)
SDA
A6
A0 R/W ACK D7
D0 ACK
D7 D6
D1 D0 ACK
I²C Device Address and
Read/Write Bit
First Data
Byte
Other
Last Data Byte
Data Bytes
Figure 77. Multiple Byte Read Transfer
Stop
Condition
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