THS7353_15 Datasheet, PDF (37/57 Pages) Texas Instruments – 3-Channel Low Power Video Buffer with I2C Control, Selectable Filters, External Gain Control, 2:1 Input MUX, and Selectable Input Modes

THS7353
www.ti.com
SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012
I²C DESIGN NOTES: ISSUES AND SOLUTIONS
The THS7353 requires some special attention to the I²C function that is usually not required. These are known
design issues, but there are simple workarounds that allow the THS7353 to perform within any I²C system.
The first known I²C issue is with respect to the power-up condition. On power up, the THS7353 registers are in a
random state from device to device. The registers remain in this random state until a valid write sequence is
made to the THS7353. A total of nine bytes of data completely configure all channels of the THS7353. Therefore,
configuring the THS7353 should be done on power-up of the system. Note that one such random state
(acknowledge state or ACK) can be engaged. While ACK is engaged, the THS7353 pulls the SDA line low and
the master cannot send data to any device on the I²C bus. To circumvent this state, at least one SCL cycle must
be completed and then the acknowledge state disengages.
While one SCL cycle normally eliminates any issues, the internal FIFO buffer may have random bits internally to
the THS7353. To completely clear all eight bits of this buffer, run eight cycles (or 8 bits or 1 byte) on the SCL
line. While there are several different methods to run SCL cycles, the simplest is to have the master send a 00h
code to the I²C bus on power-up, ignoring any ACK state. Note that the SCL cycle should occur only after the
power-supply voltage of the THS7353 is at least 2.7 V. Failure to follow this step may cause the THS7353 to
ignore the SCL cycles.
Another known issue with the I²C function is that the internal SDA and SCL buffers are susceptible to high-
frequency noise. This noise can come from switch-mode power supplies, digital processors, or other high-
frequency noise generators. While the THS7353 includes buffers with hysteresis on the front-end, these are
placed after a low-gain CMOS buffer used as an ESD protection element. The noise susceptibility in real-world
systems is very low; however, it can be an issue in some noisy or compact systems. The simple solution, which
has shown to solve the issue, is to place a RC filter on each I²C line. Real-world results show that using a 100-Ω
resistor in series on each SDA and SCL line along with a 22-pF capacitor from each SDA or SCL line to ground
eliminates the noise susceptibility issue. These RC filters should be placed as close as possible to the THS7353
SDA and SCL input pins. Other solutions have shown that not using a series resistor and only using a larger
value capacitor (such as 100 pF to 220 pF) has worked, but the RC solution is more robust.
One last real-world issue that has appeared relates to the value of the pull-up resistor on the SDA and SCL lines.
While the standard allows for between 2 kΩ and 19 kΩ for this pull-up resistor, practice has shown that keeping
this value lower works best. Typical values should be between 2 kΩ and 3.3 kΩ, with 2.7 kΩ being the most
common.
SLAVE ADDRESS
Both the SDA and the SCL must be connected to a positive supply voltage via a pullup resistor. These resistors
should comply with the I²C specification that ranges from 2 kΩ to 19 kΩ. When the bus is free, both lines are
high. The address byte is the first byte received following the START condition from the master device. The first
5 Bits (MSBs) of the address are factory preset to 01011. The next two bits of the THS7353 address are
controlled by the logic levels appearing on the I²C-A1 and I²C-A0 pins. The I²C-A1 and I²C-A0 address inputs
can be connected to V_S+ for logic 1, GND for logic 0, or it can be actively driven by TTL/CMOS logic levels. The
device address is set by the state of these pins and is not latched. Thus, a dynamic address control system can
be used to incorporate several devices on the same system. Up to four THS7353 devices can be connected to
the same I²C-Bus without requiring additional glue logic. Table 1 lists the possible addresses for the THS7353.
Bit 7 (MSB)
0
0
0
0
0
0
0
0
Bit 6
1
1
1
1
1
1
1
1
Table 1. THS7353 Slave Addresses
FIXED ADDRESS
Bit 5
0
0
0
0
0
0
0
0
Bit 4
1
1
1
1
1
1
1
1
Bit 3
1
1
1
1
1
1
1
1
SELECTABLE WITH
ADDRESS PINS
Bit 2 (A1)
Bit 1 (A0)
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
READ/WRITE
BIT
Bit 0
0
1
0
1
0
1
0
1
Copyright © 2005–2012, Texas Instruments Incorporated
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