THS7353_15 Datasheet, PDF (38/57 Pages) Texas Instruments – 3-Channel Low Power Video Buffer with I2C Control, Selectable Filters, External Gain Control, 2:1 Input MUX, and Selectable Input Modes

THS7353
SLOS484B – NOVEMBER 2005 – REVISED AUGUST 2012
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Channel Selection Register Description (Subaddress)
The THS7353 operates using only a single byte transfer protocol similar to Figure 74 and Figure 76. The internal
subaddress registers and the functionality of each are found in Table 2. When writing to the device, it is required
to send one byte of data to the corresponding internal subaddress. If control of all three channels is desired, then
the master has to cycle through all the subaddresses (channels) one at a time, see the example section, Writing
to the THS7353 for the proper procedure of writing to the THS7353.
During a read cycle, the THS7353 sends the data in its selected subaddress (or channel) in a single transfer to
the master device requesting the information. See the example section, Reading from the THS7353 for the
proper procedure on reading from the THS7353.
On power up, the THS7353 registers are in a random state from part-to-part. It remains in this random state until
a valid write sequence is made to the THS7353. A total of 9 bytes of data completely configures all channels of
the THS7353. As such, configuring the THS7353 should be done on power-up of the system. Note that one such
random state (acknowledge state) can be engaged. To circumvent this state, have one SCL cycle run, and the
acknowledge state disengages.
Table 2. THS7353 Channel Selection Register Bit Assignments
REGISTER NAME
Channel 1
Channel 2
Channel 3
BIT ADDRESS
(b7b6b5....b0)
0000 0001
0000 0010
0000 0011
38
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