THS1007_14 Datasheet, PDF (4/34 Pages) Texas Instruments – 10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS1007
SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, V_REF = internal, f_s = 6 MSPS, f_I = 2 MHz at −1 dBFS (unless otherwise noted)
AC SPECIFICATIONS, AV_DD = DV_DD = 5 V, BV_DD = 3.3 V, C_L < 30 pF
PARAMETER
TEST CONDITIONS
MIN TYP
SINAD Signal-to-noise ratio + distortion
Differential mode
Single-ended mode
56
59
55
58
SNR Signal-to-noise ratio
Differential mode
Single-ended mode
59
61
58
60
THD Total harmonic distortion
Differential mode
−64
Single-ended mode
−63
ENOB
(SNR)
Effective number of bits
Differential mode
Single-ended mode
9 9.5
8.85 9.35
SFDR Spurious free dynamic range
Differential mode
Single-ended mode
61
65
60
64
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in
differential configuration.
Full scale sinewave, −3 dB
96
Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration.
Full scale sinewave, −3 dB
54
Small-signal bandwidth with a source impedance of 150 Ω in
differential configuration.
100 mVpp sinewave, −3 dB
96
Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration.
100 mVpp sinewave, −3 dB
54
MAX
−61
−60
UNIT
dB
dB
dB
dB
dB
dB
Bits
Bits
dB
dB
MHz
MHz
MHz
MHz
TIMING REQUIREMENTS
AV_DD = DV_DD = 5 V, BV_DD = 3.3 V, V_REF = internal, C_L < 30 pF
PARAMETER
t_pipe
t_{su(CONV_CLKL-READL)}
t_{su(READH-CONV_CLKL)}
t_{d(CONV_CLKL-SYNCL)}
t_{d(CONV_CLKL-SYNCH)}
Latency
Setup time, CONV_CLK low before CS valid
Setup time, CS invalid to CONV_CLK low
Delay time, CONV_CLK low to SYNC low
Delay time, CONV_CLK low to SYNC high
TEST CONDITIONS
MIN TYP MAX UNIT
5
CONV
CLK
10
ns
20
ns
10 ns
10 ns
4