THS1007_14 Datasheet, PDF (26/34 Pages) Texas Instruments – 10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS1007
SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
www.ti.com
Read Timing (using R/W, CS0-controlled)
Figure 34 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The reading of the data
should be done with a certain timing relative to the conversion clock CONV_CLK, as illustrated in Figure 34.
CONV_CLK
10%
t _{su(CONV_CLKL−CS0L)}
t _{su(CS0H−CONV_CLKL)}
10%
CS0
10%
t_w(CS)
10%
90%
CS1
R/W^{ÓÓÓÓÓÓÓÓ90%}
RD
D(O−11)
t_su(R/W)
ta
90%
t_h(R/W)
90_ÔÔ% _{ÔÔÔÔÔÔ}
th
90%
Figure 34. Read Timing Diagram Using R/W (CS0-controlled)
Read Timing Parameter (CS0-controlled)^†
PARAMETER
t_{su(CONV_CLKL−CSOL)}
t_{su(CSOH−CONV_CLKL)}
t_su(R/W)
t_a
t_h
t_h(R/W)
t_w(CS)
Setup time, CONV_CLK low before CS valid
Setup time, CS invalid to CONV_CLK low
Setup time, R/W high to last CS valid
Access time, last CS valid to data valid
Hold time, first CS invalid to data invalid
Hold time, first external CS invalid to R/W change
Pulse duration, CS active
MIN TYP MAX UNIT
10
ns
20
ns
0
ns
0
10 ns
0
5 ns
5
ns
10
ns
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