THS1007_14 Datasheet, PDF (27/34 Pages) Texas Instruments – 10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

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THS1007
SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
Write Timing (using R/W, CS0-controlled)
Figure 35 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write
input R/W. The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled
because CS0 is the last external signal of CS0, CS1, and R/W which becomes valid. The write into the THS1007
can be performed irrespective of the conversion clock signal CONV_CLK.
t_w(CS)
CS0
10%
10%
90%
CS1
ÔÔÔ _R/W
ÔÔÔ^10%
t_su(R/W)
t_h(R/W)
ÓÓÓÓÓÓ _10%
RD
D(0−11)
t_su
90%
t_h
90%
Figure 35. Write Timing Diagram Using R/W (CS0-controlled)
Read Timing Parameter (CS0-controlled)^†
PARAMETER
t_su(R/W)
t_su
t_h
t_h(R/W)
t_w(CS)
Setup time, R/W stable to last CS valid
Setup time, data valid to first CS invalid
Hold time, first CS invalid to data invalid
Hold time, first CS invalid to R/W change
Pulse duration, CS active
MIN TYP MAX UNIT
0
ns
5
ns
2
ns
5
ns
10
ns
27