THS1007_14 Datasheet, PDF (17/34 Pages) Texas Instruments – 10-BIT, 4 ANALOG INPUT, 6-MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

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Sample N
Channel 1, 2
Sample N+1
Channel 1, 2
AIN
t_d(A)
t_{w(CONV_CLKH)}
t_d(pipe)
t_{w(CONV_CLKL)}
CONV_CLK
t_c
t_{su(CONV_CLKL-READL)}
THS1007
SLAS286B − AUGUST 2000− REVISED DECEMBER 2010
Sample N+2
Channel 1, 2
Sample N+3
Channel 1, 2
t_{su(READH-CONV_CLKL)}
READ^†
SYNC
t_{d(CONV_CLKL-SYNCL)}
t_{d(CONV_CLKL-SYNCH)}
Data N−2
Channel 1
Data N−2
Channel 2
Data N−1
Channel 1
Data N−1
Channel 2
Data N
Channel 1
Data N
Channel 2
Data N+1
Channel 1
†_{READ is the logical combination from CS0, CS1 and RD}
Figure 29. Conversion Timing in 2-Channel Operation
Figure 30 shows the conversion timing when three analog input channels are selected. The maximum
throughput rate per channel is 2 MSPS in this mode. The data flow in the bottom of the figure shows in which
order the converted data is available to the data bus. The SYNC signal is active low when the data of channel
one is available to the data bus. The data of channel one is followed by the data of channel two and channel
three before channel one is again available and the SYNC signal is active low.
Sample N
Channel 1, 2, 3
Sample N+1
Channel 1, 2, 3
Sample N+2
Channel 1, 2, 3
AIN
t_d(A)
t_d(pipe)
t_{w(CONV_CLKH)}
t_{w(CONV_CLKL)}
CONV_CLK
t_c
t_{su(CONV_CLKL-READL)}
t_{su(READH-CONV_CLKL)}
READ^†
t_{d(CONV_CLKL-SYNCL)}
t_{d(CONV_CLKL-SYNCH)}
SYNC
Data N−2
Channel 3
Data N−1
Channel 1
Data N−1
Channel 2
Data N−1
Channel 3
Data N
Channel 1
Data N
Channel 2
Data N
Channel 3
†_{READ is the logical combination from CS0, CS1 and RD}
Figure 30. Conversion Timing in 3-Channel Operation
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