DS80PCI800SQ Datasheet, PDF (4/45 Pages) Texas Instruments – DS80PCI800 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 8 Channel PCI Express Repeater

DS80PCI800
SNLS334E – APRIL 2011 – REVISED MARCH 2012
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Pin Descriptions (continued)
Pin Name
Pin Number
OUTB_0+, OUTB_0-,
OUTB_1+, OUTB_1-,
OUTB_2+, OUTB_2-,
OUTB_3+, OUTB_3-,
45, 44, 43, 42,
40, 39, 38, 37
OUTA_0+, OUTA_0-,
OUTA_1+, OUTA_1-,
OUTA_2+, OUTA_2-,
OUTA_3+, OUTA_3-
35, 34, 33, 32,
31, 30, 29, 28
Control Pins — Shared (LVCMOS)
ENSMB
48
I/O, Type
O
O
I, FLOAT,
LVCMOS
ENSMB = 1 (SMBUS MODE)
SCL
50
SDA
49
AD0-AD3
54, 53, 47, 46
I, LVCMOS
O, OPEN Drain
I, LVCMOS,
O, OPEN Drain
I, LVCMOS
READ_EN
26
ENSMB = 0 (PIN MODE)
EQA0, EQA1,
EQB0, EQB1
20, 19,
46, 47
I, LVCMOS
I, 4-LEVEL,
LVCMOS
DEMA0, DEMA1,
DEMB0, DEMB1
49, 50,
53, 54
I, 4-LEVEL,
LVCMOS
RATE
21
I, 4-LEVEL,
LVCMOS
SD_TH
26
I, 4-LEVEL,
LVCMOS
Control Pins — Both Pin and SMBus Modes (LVCMOS)
RXDET
22
I, 4-LEVEL,
LVCMOS
RESERVED
23
VDD_SEL
25
I, FLOAT
I, FLOAT
PRSNT
52
I, LVCMOS
Pin Description
Inverting and non-inverting 50Ω driver bank A outputs with de-emphasis.
Compatible with AC coupled CML inputs.
Inverting and non-inverting 50Ω driver bank A outputs with de-emphasis.
Compatible with AC coupled CML inputs.
System Management Bus (SMBus) enable pin
Tie 1kΩ to VDD = Register Access SMBus Slave Mode
FLOAT = Read External EEPROM (Master SMBUS Mode)
Tie 1kΩ to GND = Pin Mode
ENSMB Master or Slave mode
SMBUS clock input is enabled (slave mode).
Clock output when loading EEPROM configuration (master mode).
ENSMB Master or Slave mode
The SMBus bi-directional SDA pin is enabled. Data input or open drain
(pull-down only) output.
ENSMB Master or Slave mode
SMBus Slave Address Inputs. In SMBus mode, these pins are the user
set SMBus slave address inputs.
When using an External EEPROM, a transition from high to low starts
the load from the external EEPROM
EQA[1:0] and EQB[1:0] control the level of equalization on the input pins.
The pins are active only when ENSMB is de-asserted (low). The 8
channels are organized into two banks. Bank A is controlled with the
EQA[1:0] pins and bank B is controlled with the EQB[1:0] pins. When
ENSMB goes high the SMBus registers provide independent control of
each channel. The EQB[1:0] pins are converted to SMBUS AD2/AD3
inputs. See Table 2.
DEMA[1:0] and DEMB[1:0] control the level of de-emphasis of the output
driver when in Gen1/2 mode. The pins are only active when ENSMB is
de-asserted (low). The 8 channels are organized into two banks. Bank A
is controlled with the DEMA[1:0] pins and bank B is controlled with the
DEMB[1:0] pins. When ENSMB goes high the SMBus registers provide
independent control of each channel. The DEMA[1:0] pins are converted
to SMBUS SCL/SDA and DEMB[1:0] pins are converted to AD0, AD1
inputs.
See Table 3.
RATE control pin selects GEN 1,2 and GEN 3 operating modes.
Tie 1kΩ to GND = GEN 1,2
FLOAT = AUTO Rate Select
Tie 20kΩ to GND = GEN 3 without De-emphasis
Tie 1kΩ to VDD = GEN 3 with De-emphasis
Controls the internal Signal Detect Threshold.
See Table 5.
The RXDET pin controls the receiver detect function. Depending on the
input level, a 50Ω or >50kΩ termination to the power rail is enabled.
See Table 4.
Float (leave pin open) = Normal Operation
Controls the internal regulator
FLOAT = 2.5V mode
Tie GND = 3.3V mode
Cable Present Detect input. high when a cable is not present per PCIe
Cabling Spec. 1.0. Puts part into low power mode. When LOW (normal
operation) part is enabled.
See Table 4.
4
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