DS80PCI800SQ Datasheet, PDF (15/45 Pages) Texas Instruments – DS80PCI800 2.5 Gbps / 5.0 Gbps / 8.0 Gbps 8 Channel PCI Express Repeater

DS80PCI800
www.ti.com
0
Float
(Default)
0
1
1
X
SNLS334E – APRIL 2011 – REVISED MARCH 2012
Table 4. RX-Detect Settings (continued)
10
High Impedance High Z until recevier Auto RX-Detect, outputs test every 12 msec
50 Ω
is detected
until detection occurs; termination is high-z
until detection; once detected input termination
is 50 Ω
11
50 Ω
X
Manual RX-Detect, input is 50 Ω
High Impedance
X
Power down mode, input is high impedance,
output drivers are disabled
Used to reset RX-Detect State Machine when
held high for 5 usec
Table 5. Signal Detect Threshold Level⁽¹⁾
SD_TH
0
R
F (default)
1
SMBus REG bit [3:2] and [1:0]
10
01
00
11
Assert Level (typ)
210 mVp-p
160 mVp-p
180 mVp-p
190 mVp-p
(1) VDD = 2.5V, 25°C and 0101 pattern at 8 Gbps
De-assert Level (typ)
150 mVp-p
100 mVp-p
110 mVp-p
130 mVp-p
SMBUS Master Mode
The DS80PCI800 devices support reading directly from an external EEPROM device by implementing SMBus
Master mode. When using the SMBus master mode, the DS80PCI800 will read directly from specific location in
the external EEPROM. When designing a system for using the external EEPROM, the user needs to follow these
specific guidelines.
• Set ENSMB = Float — enable the SMBUS master mode.
• The external EEPROM device address byte must be 0xA0'h and capable of 400 kHz operation at 2.5V and
3.3V supply.
• Set the AD[3:0] inputs for SMBus address byte. When the AD[3:0] = 0000'b, the device address byte is B0'h.
When tying multiple DS80PCI800 devices to the SDA and SCL bus, use these guidelines to configure the
devices.
• Use SMBus AD[3:0] address bits so that each device can loaded it's configuration from the EEPROM.
Example below is for 4 device.
– U1: AD[3:0] = 0000 = 0xB0'h,
– U2: AD[3:0] = 0001 = 0xB2'h,
– U3: AD[3:0] = 0010 = 0xB4'h,
– U4: AD[3:0] = 0011 = 0xB6'h
• Use a pull-up resistor on SDA and SCL; value = 2k ohms
• Daisy-chain READEN# (pin 26) and ALL_DONE# (pin 27) from one device to the next device in the sequence
so that they do not compete for the EEPROM at the same time.
– 1. Tie READEN# of the 1st device in the chain (U1) to GND
– 2. Tie ALL_DONE# of U1 to READEN# of U2
– 3. Tie ALL_DONE# of U2 to READEN# of U3
– 4. Tie ALL_DONE# of U3 to READEN# of U4
– 5. Optional: Tie ALL_DONE# output of U4 to a LED to show the devices have been loaded successfully
Below is an example of a 2 kbits (256 x 8-bit) EEPROM in hex format for the DS80PCI800 device. The first 3
bytes of the EEPROM always contain a header common and necessary to control initialization of all devices
connected to the I2C bus. CRC enable flag to enable/disable CRC checking. If CRC checking is disabled, a fixed
pattern (8’hA5) is written/read instead of the CRC byte from the CRC location, to simplify the control. There is a
MAP bit to flag the presence of an address map that specifies the configuration data start in the EEPROM. If the
MAP bit is not present the configuration data start address is derived from the DS80PCI800 address and the
configuration data size. A bit to indicate an EEPROM size > 256 bytes is necessary to properly address the
EEPROM. There are 37 bytes of data size for each DS80PCI800 device.
Copyright © 2011–2012, Texas Instruments Incorporated
Product Folder Links: DS80PCI800
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