TM4C1230E6PM Datasheet, PDF (341/1103 Pages) Texas Instruments – Tiva™ TM4C1230E6PM Microcontroller

Tiva^™ TM4C1230E6PM Microcontroller
Register 73: Analog-to-Digital Converter Sleep Mode Clock Gating Control
(SCGCADC), offset 0x738
The SCGCADC register provides software the capability to enable and disable the ADC modules
in sleep mode. When enabled, a module is provided a clock. When disabled, the clock is disabled
to save power. This register provides the same capability as the legacy Sleep Mode Clock Gating
Control Register n SCGCn registers specifically for the watchdog modules and has the same bit
polarity as the corresponding SCGCn bits.
Important: This register should be used to control the clocking for the ADC modules. To support
legacy software, the SCGC0 register is available. A write to the SCGC0 register also
writes the corresponding bit in this register. Any bits that are changed by writing to the
SCGC0 register can be read back correctly with a read of the SCGC0 register. If software
uses this register to write a legacy peripheral (such as ADC0), the write causes proper
operation, but the value of that bit is not reflected in the SCGC0 register. If software
uses both legacy and peripheral-specific register accesses, the peripheral-specific
registers must be accessed by read-modify-write operations that affect only peripherals
that are not present in the legacy registers. In this manner, both the peripheral-specific
and legacy registers have coherent information.
Analog-to-Digital Converter Sleep Mode Clock Gating Control (SCGCADC)
Base 0x400F.E000
Offset 0x738
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
reserved
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
reserved
S1
S0
Type RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:2
1
Name
reserved
S1
Type
RO
RW
Reset
0
0
Description
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
ADC Module 1 Sleep Mode Clock Gating Control
Value Description
0 ADC module 1 is disabled.
1 Enable and provide a clock to ADC module 1 in sleep mode.
0
S0
RW
0
ADC Module 0 Sleep Mode Clock Gating Control
Value Description
0 ADC module 0 is disabled.
1 Enable and provide a clock to ADC module 0 in sleep mode.
June 12, 2014
341
Texas Instruments-Production Data