TM4C1230E6PM Datasheet, PDF (10/1103 Pages) Texas Instruments – Tiva™ TM4C1230E6PM Microcontroller

Table of Contents
List of Figures
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Figure 3-1.
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Figure 5-6.
Figure 7-1.
Figure 7-2.
Figure 8-1.
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Figure 10-1.
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Figure 10-9.
Figure 11-1.
Figure 12-1.
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Figure 12-3.
Tiva^™ TM4C1230E6PM Microcontroller High-Level Block Diagram ......................... 38
CPU Block Diagram ............................................................................................. 57
TPIU Block Diagram ............................................................................................ 58
Cortex-M4F Register Set ...................................................................................... 61
Bit-Band Mapping ................................................................................................ 85
Data Storage ....................................................................................................... 86
Vector Table ........................................................................................................ 93
Exception Stack Frame ........................................................................................ 96
SRD Use Example ............................................................................................. 114
FPU Register Bank ............................................................................................ 117
JTAG Module Block Diagram .............................................................................. 187
Test Access Port State Machine ......................................................................... 190
IDCODE Register Format ................................................................................... 196
BYPASS Register Format ................................................................................... 196
Boundary Scan Register Format ......................................................................... 197
Basic RST Configuration .................................................................................... 201
External Circuitry to Extend Power-On Reset ....................................................... 201
Reset Circuit Controlled by Switch ...................................................................... 202
Power Architecture ............................................................................................ 205
Main Clock Tree ................................................................................................ 207
Module Clock Selection ...................................................................................... 213
Internal Memory Block Diagram .......................................................................... 446
EEPROM Block Diagram ................................................................................... 447
μDMA Block Diagram ......................................................................................... 507
Example of Ping-Pong μDMA Transaction ........................................................... 513
Memory Scatter-Gather, Setup and Configuration ................................................ 515
Memory Scatter-Gather, μDMA Copy Sequence .................................................. 516
Peripheral Scatter-Gather, Setup and Configuration ............................................. 518
Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 519
Digital I/O Pads ................................................................................................. 573
Analog/Digital I/O Pads ...................................................................................... 574
GPIODATA Write Example ................................................................................. 575
GPIODATA Read Example ................................................................................. 575
GPTM Module Block Diagram ............................................................................ 626
Reading the RTC Value ...................................................................................... 633
Input Edge-Count Mode Example, Counting Down ............................................... 635
16-Bit Input Edge-Time Mode Example ............................................................... 636
16-Bit PWM Mode Example ................................................................................ 638
CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 638
CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 639
CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 639
Timer Daisy Chain ............................................................................................. 640
WDT Module Block Diagram .............................................................................. 696
Implementation of Two ADC Blocks .................................................................... 721
ADC Module Block Diagram ............................................................................... 722
ADC Sample Phases ......................................................................................... 725
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June 12, 2014
Texas Instruments-Production Data