TM4C1230E6PM Datasheet, PDF (128/1103 Pages) Texas Instruments – Tiva™ TM4C1230E6PM Microcontroller

Cortex-M4 Peripherals
Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100
Register 5: Interrupt 32-63 Set Enable (EN1), offset 0x104
Register 6: Interrupt 64-95 Set Enable (EN2), offset 0x108
Register 7: Interrupt 96-127 Set Enable (EN3), offset 0x10C
Note: This register can only be accessed from privileged mode.
The ENn registers enable interrupts and show which interrupts are enabled. Bit 0 of EN0 corresponds
to Interrupt 0; bit 31 corresponds to Interrupt 31. Bit 0 of EN1 corresponds to Interrupt 32; bit 31
corresponds to Interrupt 63. Bit 0 of EN2 corresponds to Interrupt 64; bit 31 corresponds to Interrupt
95. Bit 0 of EN3 corresponds to Interrupt 96; bit 31 corresponds to Interrupt 127. Bit 0 of EN4 (see
page 129) corresponds to Interrupt 128; bit 10 corresponds to Interrupt 138.
See Table 2-9 on page 90 for interrupt assignments.
If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt
is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC
never activates the interrupt, regardless of its priority.
Interrupt 0-31 Set Enable (EN0)
Base 0xE000.E000
Offset 0x100
Type RW, reset 0x0000.0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
INT
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
INT
Type RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit/Field
31:0
Name
INT
Type
Reset Description
RW 0x0000.0000 Interrupt Enable
Value
0
1
Description
On a read, indicates the interrupt is disabled.
On a write, no effect.
On a read, indicates the interrupt is enabled.
On a write, enables the interrupt.
A bit can only be cleared by setting the corresponding INT[n] bit in
the DISn register.
128
June 12, 2014
Texas Instruments-Production Data