TM4C1230E6PM Datasheet, PDF (210/1103 Pages) Texas Instruments – Tiva™ TM4C1230E6PM Microcontroller

System Control
5.2.5.4
5.2.5.5
5.2.5.6
5.2.5.7
UTEN bit, then program the UT field, and then set the UPDATE bit. The adjustment finishes within
a few clock periods and is glitch free.
Crystal Configuration for the Main Oscillator (MOSC)
The main oscillator supports the use of a select number of crystals from 4 to 25 MHz.
The XTAL bit in the RCC register (see page 236) describes the available crystal choices and default
programming values.
Software configures the RCC register XTAL field with the crystal number. If the PLL is used in the
design, the XTAL field value is internally translated to the PLL settings.
Main PLL Frequency Configuration
The main PLL is disabled by default during power-on reset and is enabled later by software if
required. Software specifies the output divisor to set the system clock frequency and enables the
main PLL to drive the output. The PLL operates at 400 MHz, but is divided by two prior to the
application of the output divisor, unless the DIV400 bit in the RCC2 register is set.
To configure the PIOSC to be the clock source for the main PLL, program the OSCRC2 field in the
Run-Mode Clock Configuration 2 (RCC2) register to be 0x1.
If the main oscillator provides the clock reference to the main PLL, the translation provided by
hardware and used to program the PLL is available for software in the PLL Frequency n
(PLLFREQn) registers (see page 251). The internal translation provides a translation within ± 1% of
the targeted PLL VCO frequency. Table 20-14 on page 1071 shows the actual PLL frequency and
error for a given crystal choice.
The Crystal Value field (XTAL) in the Run-Mode Clock Configuration (RCC) register (see page 236)
describes the available crystal choices and default programming of the PLLFREQn registers. Any
time the XTAL field changes, the new settings are translated and the internal PLL settings are
updated.
PLL Modes
■ Normal: The PLL multiplies the input clock reference and drives the output.
■ Power-Down: Most of the PLL internal circuitry is disabled and the PLL does not drive the output.
The modes are programmed using the RCC/RCC2 register fields (see page 236 and page 242).
PLL Operation
If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks)
to the new setting. The time between the configuration change and relock is T_READY (see Table
20-13 on page 1071). During the relock time, the affected PLL is not usable as a clock reference.
Software can poll the LOCK bit in the PLL Status (PLLSTAT) register to determine when the PLL
has locked.
The PLL is changed by one of the following:
■ Change to the XTAL value in the RCC register—writes of the same value do not cause a relock.
■ Change in the PLL from Power-Down to Normal mode.
A counter clocked by the system clock is used to measure the T_READY requirement. The down
counter is set to 0x200 if the PLL is powering up. If the M or N values in the PLLFREQn registers
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June 12, 2014
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