TM4C1230E6PM Datasheet, PDF (1063/1103 Pages) Texas Instruments – Tiva™ TM4C1230E6PM Microcontroller

Tiva^™ TM4C1230E6PM Microcontroller
Figure 20-4. Power Assertions versus VDDA Levels
VDDAMIN
P1
P5_RISE
P4
P5_FALL
P4
1
0
1
0
1
0
20.6.2
VDD Levels
The V_DD supply has three monitors:
■ Power-OK (POK)
■ Brown-Out Reset0 (BOR0)
■ Brown-Out Reset1 (BOR1)
The POK monitor is used to keep the digital circuitry in reset until the V_DD power supply is at an
acceptable operational level. The digital Power-On Reset (Digital POR) is only released when
the Power-On Reset has deasserted and all of the Power-OK monitors for each of the supplies
indicate that power levels are in operational ranges. The BOR0 and the BOR1 monitors are used
to generate a reset to the device or assert an interrupt if the V_DD supply drops below its operational
range. The BOR1 monitor's threshold is in between the BOR0 and POK thresholds.
If either a BOR0 event or a BOR1 event occurs, the following bits are affected:
■ BOR0RIS or BOR1RIS bits in the Raw Interrupt Status (RIS) register (see page 227).
■ BOR0MIS or BOR1MIS bits in the Masked Interrupt Status and Clear (MISC) register (see
page 231). These bits are set only if the respective BOR0IM or BOR1IM bits in the Interrupt Mask
Control (IMC) register have been set.
■ BOR bit in the Reset Cause (RESC) register (see page 234). This bit is set only if either of the
BOR0 or BOR1 events have been configured to initiate a reset.
In addition, the following bits control both the BOR0 and BOR1 events:
■ BOR0IM or BOR1IM bits in the Interrupt Mask Control (IMC) register (see page 229).
June 12, 2014
Texas Instruments-Production Data
1063