MSP43020X3 Datasheet, PDF (34/92 Pages) Texas Instruments – MIXED SIGNAL MICROCONTROLLER

MSP430F20x3
MSP430F20x2
MSP430F20x1
SLAS491H – AUGUST 2005 – REVISED AUGUST 2011
www.ti.com
Crystal Oscillator, XT1, Low-Frequency Mode⁽¹⁾
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
f_LFXT1,LF
PARAMETER
LFXT1 oscillator crystal
frequency, LF mode 0, 1
TEST CONDITIONS
XTS = 0, LFXT1Sx = 0 or 1
V_CC
1.8 V to 3.6 V
MIN TYP MAX UNIT
32768
Hz
f_{LFXT1,LF,logic}
LFXT1 oscillator logic level
square wave input frequency, XTS = 0, LFXT1Sx = 3
LF mode
1.8 V to 3.6 V 10000 32768 50000 Hz
OA_LF
Oscillation allowance for
LF crystals
XTS = 0, LFXT1Sx = 0,
f_LFXT1,LF = 32768 Hz, C_L,eff = 6 pF
XTS = 0, LFXT1Sx = 0,
f_LFXT1,LF = 32768 Hz, C_L,eff = 12 pF
XTS = 0, XCAPx = 0
500
kΩ
200
1
C_L,eff
Integrated effective load
capacitance, LF mode⁽²⁾
XTS = 0, XCAPx = 1
XTS = 0, XCAPx = 2
5.5
pF
8.5
XTS = 0, XCAPx = 3
11
f_Fault,LF
Duty cycle, LF mode
Oscillator fault frequency,
LF mode⁽³⁾
XTS = 0, Measured at P1.0/ACLK,
f_LFXT1,LF = 32768 Hz
XTS = 0, LFXT1Sx = 3⁽⁴⁾
2.2 V/3 V
2.2 V/3 V
30
50
70 %
10
10000 Hz
(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.
(a) Keep the trace between the device and the crystal as short as possible.
(b) Design a good ground plane around the oscillator pins.
(c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.
(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.
(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).
Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a
correct setup, the effective load capacitance should always match the specification of the used crystal.
(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.
Frequencies in between might set the flag.
(4) Measured with logic-level input frequency but also applies to operation with crystals.
Internal Very-Low-Power Low-Frequency Oscillator (VLO)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
f_VLO
VLO frequency
T_A
-40°C to 85°C
105°C
V_CC
2.2 V/3 V
MIN TYP
4
12
df_VLO/dT
VLO frequency temperature drift⁽¹⁾
I: -40°C to 85°C
T: -40°C to 105°C
2.2 V/3 V
0.5
df_VLO/dV_CC
VLO frequency supply voltage drift⁽²⁾
25°C
1.8 V to 3.6 V
4
(1) Calculated using the box method:
I: (MAX(-40 to 85°C) - MIN(-40 to 85°C)) / MIN(-40 to 85°C) / (85°C - (-40°C))
T: (MAX(-40 to 105°C) - MIN(-40 to 105°C)) / MIN(-40 to 105°C) / (105°C - (-40°C))
(2) Calculated using the box method: (MAX(1.8 to 3.6 V) - MIN(1.8 to 3.6 V)) / MIN(1.8 to 3.6 V) / (3.6 V - 1.8 V)
MAX
20
22
UNIT
kHz
%/°C
%/V
Timer_A
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
f_TA
Timer_A clock frequency
TEST CONDITIONS
Internal: SMCLK, ACLK
External: TACLK, INCLK
Duty cycle = 50% ± 10%
V_CC
2.2 V
3V
MIN TYP
t_TA,cap
Timer_A capture timing
TA0, TA1
2.2 V/3 V
20
MAX
10
16
UNIT
MHz
ns
34
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