LP3921 Datasheet, PDF (34/41 Pages) National Semiconductor (TI) – Battery Charger Management and Regulator Unit with Integrated Boomer® Audio Amplifier

LP3921
SNVS580A – AUGUST 2008 – REVISED MAY 2013
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• Write cycle ends when the master creates stop condition.
CONTROL REGISTER READ CYCLE
• Master device generates a start condition.
• Master device sends slave address (7 bits) and the data direction bit (R/W = “0”).
• Slave device sends acknowledge signal if the slave address is correct.
• Master sends control register address (8 bits).
• Slave sends acknowledge signal.
• Master device generates repeated start condition.
• Master sends the slave address (7 bits) and the data direction bit (R/W = “1”).
• Slave sends acknowledge signal if the slave address is correct.
• Slave sends data byte from addressed register.
• If the master device sends acknowledge signal, the control register address will be incremented by one. Slave
device sends data byte from addressed register.
• Read cycle ends when the master does not generate acknowledge signal after data byte and generates stop
condition.
Table 24. I²C Read/Write Sequences⁽¹⁾
Data Read
Data Write
Address Mode
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Repeated Start Condition>
<Slave Address><r/w = ‘1’>[Ack]
[Register Date]<Ack or nAck>
… additional reads from subsequent register address possible
<Stop Condition>
<Start Condition>
<Slave Address><r/w = ‘0’>[Ack]
<Register Addr.>[Ack]
<Register Data>[Ack]
… additional writes to subsequent register address possible
<Stop Condition>
(1) < > Data from master [ ] Data from slave
REGISTER READ AND WRITE DETAIL
Slave Address
Control Register Add.
S
(7 bits)
'0' A
(8 bits)
A
Register Data
(8 bits)
AP
R/W
Data transferred, byte +
Ack
From Slave to Master
From Master to Slave
A - ACKNOWLEDGE (SDA Low)
S - START CONDITION
P - STOP CONDITION
Figure 14. Register Write Format
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