LP3921 Datasheet, PDF (13/41 Pages) National Semiconductor (TI) – Battery Charger Management and Regulator Unit with Integrated Boomer® Audio Amplifier

LP3921
www.ti.com
SNVS580A – AUGUST 2008 – REVISED MAY 2013
Audio Electrical Characteristics
Unless otherwise noted, V_DD= 3.6V Typical values and limits appearing in normal type apply for T_J = 25°C. Limits appearing in
boldface type apply over the entire junction temperature range for operation, T_A= T_J = −25°C to +85°C. ⁽¹⁾
Symbol
Paramater
Conditions
Typical
Limit
Min
Max
Units
P_O
Output Power
THD = 1% (max);
0.375
W
f = 1 kHz, R_L = 8Ω
THD + N
Total Harmonic Distortion P_O = 0.25 Wrms;
0.02
%
+ Noise
f = 1 kHz
Vripple = 200 mV_PP
PSRR
Power Supply Rejection
Ratio
f = 217 Hz
85
f = 1 kHz
85
dB
73
CMRR
Common-Mode Rejection f = 217 Hz,
50
dB
Ratio
V_CM = 200 mV_PP
V_OS
Output Offset
Vac_INput = 0V
4
mV
(1) All limits are verified. All electrical characteristics having room-temperature limits are tested during production with T_J = 25°C. All hot and
cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process
control.
Serial Interface
Unless otherwise noted, V_IN ( = VIN1 = VIN2 = BATT=VDD) = 3.6V, GND = 0V, C_VIN1-2=10 µF, C_LDOX=1 µF, and V_LDO2 (DIGI)
≥ 1.8V. Typical values and limits appearing in normal type apply for T_J = 25°C. Limits appearing in boldface type apply over
the entire junction temperature range for operation, T_A= T_J = −40°C to +125°C. ^{(1) (2)}
Symbol
Parameter
Condition
Limit
Typ
Units
Min
Max
f_CLK
Clock Frequency
t_BF
Bus-Free Time between
START and STOP
400
kHz
1.3
µs
t_HOLD
Hold Time Repeated START
Condition
0.6
µs
t_CLK-LP
t_CLK-HP
t_SU
CLK Low Period
CLK High Period
Set-Up Time Repeated
START Condition
1.3
µs
0.6
µs
0.6
µs
t_DATA-HOLD
t_DATA-SU
t_SU
Data Hold Time
Data Set-Up Time
Set-Up Time for STOP
Condition
50
ns
100
ns
0.6
µs
t_TRANS
Maximum Pulse Width of
50
ns
Spikes that Must be
Suppressed by the Input
Filter of both DATA & CLK
Signals
(1) All limits are verified. All electrical characteristics having room-temperature limits are tested during production with T_J = 25°C. All hot and
cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process
control.
(2) Specified by design.
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