LP3921 Datasheet, PDF (15/41 Pages) National Semiconductor (TI) – Battery Charger Management and Regulator Unit with Integrated Boomer® Audio Amplifier

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CHG_IN
HF_PWR
320 ms
PS_HOLD
LP3921
SNVS580A – AUGUST 2008 – REVISED MAY 2013
If charger is connected (CHG_IN) or HF_PWR is
applied, then both events are filtered for 320 ms
before enabling LDO1
PS_HOLD needs to be asserted within 1200 ms after
CHG_IN or HF_PWR rising edge has been detected.
(HF_PWR level detected for LP3921)
1.2s
Debounce time before normal start up sequence, 320 ms.
PS_HOLD high < 1.2s from I/P detection
LDO1
LDO2
RESET
LDO3
87% Reg
< 200 Ps
87% Reg
60 ms
I²C Control
LDO7
RX_EN, TX_EN,
TCXO_EN
LDO4,5,6
Note: Serial I/F commands only take place
after PS_HOLD is asserted.
Figure 3. Device Power Up Logic Timing: CHG_IN, HF_PWR
START UP
Device start is initiated by any of the 3 input signals, PWR_ON, HF_PWR and CHG_IN.
PWR_ON
When PWR_ON goes high the device will remain powered up, a PS_HOLD applied will allow the device to
remain powered after the PWR_ON signal has gone low.
HF_PWR, CHGIN
PS_HOLD needs to be asserted within 1200 ms after a CHG_IN or HF_PWR rising edge has been detected. For
applications where a level sensitive input is required the LP3921 is available with a level detect input at
HF_PWR.
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