TCA9539_15 Datasheet, PDF (30/42 Pages) Texas Instruments – Low Voltage 16-Bit I2C and SMBus Low-Power I/O Expander

TCA9539
SCPS202B – OCTOBER 2009 – REVISED OCTOBER 2015
11 Layout
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11.1 Layout Guidelines
For printed circuit board (PCB) layout of the TCA9554A, common PCB layout practices should be followed but
additional concerns related to high-speed data transfer such as matched impedances and differential pairs are
not a concern for I²C signal speeds.
In all PCB layouts, it is a best practice to avoid right angles in signal traces, to fan out signal traces away from
each other upon leaving the vicinity of an integrated circuit (IC), and to use thicker trace widths to carry higher
amounts of current that commonly pass through power and ground traces. By-pass and de-coupling capacitors
are commonly used to control the voltage on the VCC pin, using a larger capacitor to provide additional power in
the event of a short power supply glitch and a smaller capacitor to filter out high-frequency ripple. These
capacitors should be placed as close to the TCA9554A as possible. These best practices are shown in
Figure 42.
For the layout example provided in Figure 42, it would be possible to fabricate a PCB with only 2 layers by using
the top layer for signal routing and the bottom layer as a split plane for power (V_CC) and ground (GND). However,
a 4 layer board is preferable for boards with higher density signal routing. On a 4 layer PCB, it is common to
route signals on the top and bottom layer, dedicate one internal layer to a ground plane, and dedicate the other
internal layer to a power plane. In a board layout using planes or split planes for power and ground, vias are
placed directly next to the surface mount component pad which needs to attach to V_CC or GND and the via is
connected electrically to the internal layer or the other side of the board. Vias are also used when a signal trace
needs to be routed to the opposite side of the board, but this technique is not demonstrated in Figure 42.
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