TCA9539_15 Datasheet, PDF (28/42 Pages) Texas Instruments – Low Voltage 16-Bit I2C and SMBus Low-Power I/O Expander

TCA9539
SCPS202B – OCTOBER 2009 – REVISED OCTOBER 2015
10 Power Supply Recommendations
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10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, TCA9539 can be reset to its default conditions by using the power-on
reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This
reset also happens when the device is powered on for the first time in an application.
The voltage waveform for a power-on reset is shown in Figure 39.
V_CC
Ramp-Down
Ramp-Up
V_CC drops below V_PORF – 50 mV
V_{CC_TRR}
V_{CC_FT}
Time to Re-Ramp
V_{CC_RT}
V_CC Is lowered below the POR threshold, then ramped back up to V_CC
Figure 39. Voltage Waveform for Power-On Reset
Time
Table 8 specifies the performance of the power-on reset feature for TCA9539.
Table 8. Recommended Supply Sequencing and Ramp Rates ⁽¹⁾
V_{CC_FT}
V_{CC_RT}
V_{CC_TRR}
V_{CC_GH}
V_{CC_GW}
PARAMETER
Fall rate
See Figure 39
Rise rate
See Figure 39
Time to re-ramp (when V_CC drops to V_{POR_MIN} – 50 mV or when
V_CC drops to GND)
See Figure 39
Level that V_CC can glitch down to, but not cause a functional
disruption when V_{CC_GW} = 1 μs
See Figure 40
Glitch width that will not cause a functional disruption when
V_{CC_GH} = 0.5 × V_CC (For V_CC > 3.0 V)
See Figure 40
MIN TYP
0.22
0.15
MAX
UNIT
ms
ms
1
μs
1.2 V
10 μs
(1) T_A = –40°C to 85°C (unless otherwise noted)
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width
(V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and
device impedance are factors that affect power-on reset performance. Figure 40 and Table 8 provide more
information on how to measure these specifications.
V_CC
V_{CC_GH}
V_{CC_GW}
Figure 40. Glitch Width and Glitch Height
Time
V_POR is critical to the power-on reset. V_PORR is the voltage level at which the reset condition is released and all
the registers and the I²C/SMBus state machine are initialized to their default states. The value of V_POR differs
based on the V_CC being lowered to or from 0. Figure 41 and Table 8 provide more details on this specification.
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