TCA9539_15 Datasheet, PDF (17/42 Pages) Texas Instruments – Low Voltage 16-Bit I2C and SMBus Low-Power I/O Expander

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Functional Block Diagram (continued)
Data From
Shift Register
Data From
Shift Register
Write Configuration
Pulse
Configuration
Register
DQ
FF
CLK Q
Write Pulse
DQ
FF
CLK Q
Output Port
Register
Read Pulse
TCA9539
SCPS202B – OCTOBER 2009 – REVISED OCTOBER 2015
Output Port
Register Data
V_CC
Q1
Input Port
Register
DQ
FF
CLK Q
I/O Pin
Q2
GND
Input Port
Register Data
To INT
Data From
Shift Register
DQ
FF
Write Polarity
Pulse
CLK Q
Polarity Inversion
Register
(1) At power-on reset, all registers return to default values.
Figure 23. Simplified Schematic of P-Port I/Os
Polarity
Register Data
8.3 Feature Description
8.3.1 I/O Port
When an I/O is configured as an input, FETs Q1 and Q2 are off, which creates a high-impedance input. The
input voltage may be raised above V_CC to a maximum of 5.5 V.
If the I/O is configured as an output, Q1 or Q2 is enabled, depending on the state of the Output Port register. In
this case, there are low-impedance paths between the I/O pin and either V_CC or GND. The external voltage
applied to this I/O pin should not exceed the recommended levels for proper operation.
8.3.2 RESET Input
A reset can be accomplished by holding the RESET pin low for a minimum of t_W. The TCA9539 registers and
I²C/SMBus state machine are held in their default states until RESET is once again high. This input requires a
pullup resistor to V_CC, if no active connection is used.
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