TCA9539_15 Datasheet, PDF (18/42 Pages) Texas Instruments – Low Voltage 16-Bit I2C and SMBus Low-Power I/O Expander

TCA9539
SCPS202B – OCTOBER 2009 – REVISED OCTOBER 2015
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Feature Description (continued)
8.3.3 Interrupt (INT) Output
An interrupt is generated by any rising or falling edge of the port inputs in the input mode. After time, t_iv, the
signal INT is valid. Resetting the interrupt circuit is achieved when data on the port is changed to the original
setting or data is read from the port that generated the interrupt. Resetting occurs in the read mode at the
acknowledge (ACK) bit or not acknowledge (NACK) bit after the falling edge of the SCL signal. Interrupts that
occur during the ACK or NACK clock pulse can be lost (or be very short) due to the resetting of the interrupt
during this pulse. Each change of the I/Os after resetting is detected and is transmitted as INT.
Reading from or writing to another device does not affect the interrupt circuit, and a pin configured as an output
cannot cause an interrupt. Changing an I/O from an output to an input may cause a false interrupt to occur if the
state of the pin does not match the contents of the Input Port register. Because each 8-bit port is read
independently, the interrupt caused by port 0 is not cleared by a read of port 1, or vice versa.
INT has an open-drain structure and requires a pullup resistor to V_CC.
8.4 Device Functional Modes
8.4.1 Power-On Reset
When power (from 0 V) is applied to VCC, an internal power-on reset holds the TCA9539 in a reset condition
until V_CC has reached V_{POR R}. At that point, the reset condition is released and the TCA9539 registers and
I²C/SMBus state machine initialize to their default states. After that, V_CC must be lowered to below V_PORF and
then back up to the operating voltage for a power-reset cycle.
8.5 Programming
8.5.1 I²C Interface
The TCA9539 has a standard bidirectional I²C interface that is controlled by a master device in order to be
configured or read the status of this device. Each slave on the I²C bus has a specific device address to
differentiate between other slave devices that are on the same I²C bus. Many slave devices will require
configuration upon startup to set the behavior of the device. This is typically done when the master accesses
internal register maps of the slave, which have unique register addresses. A device can have one or multiple
registers where data is stored, written, or read. For more information see Understanding the I²C Bus, (SLVA704).
The physical I²C interface consists of the serial clock (SCL) and serial data (SDA) lines. Both SDA and SCL lines
must be connected to V_CC through a pull-up resistor. The size of the pull-up resistor is determined by the amount
of capacitance on the I²C lines. For further details, refer to I²C Pull-up Resistor Calculation (SLVA689). Data
transfer may be initiated only when the bus is idle. A bus is considered idle if both SDA and SCL lines are high
after a STOP condition.
The following is the general procedure for a master to access a slave device:
1. If a master wants to send data to a slave:
– Master-transmitter sends a START condition and addresses the slave-receiver.
– Master-transmitter sends data to slave-receiver.
– Master-transmitter terminates the transfer with a STOP condition.
2. If a master wants to receive or read data from a slave:
– Master-receiver sends a START condition and addresses the slave-transmitter.
– Master-receiver sends the requested register to read to slave-transmitter.
– Master-receiver receives data from the slave-transmitter.
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