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TCA9539_15 Datasheet, PDF (24/42 Pages) Texas Instruments – Low Voltage 16-Bit I2C and SMBus Low-Power I/O Expander
TCA9539
SCPS202B – OCTOBER 2009 – REVISED OCTOBER 2015
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Data is clocked into the register on the rising edge of the ACK clock pulse. There is no limitation on the number
of data bytes received in one read transmission, but when the final byte is received, the bus master must not
acknowledge the data.
SCL
123456789
10.x
11.x
10.x
11.x
SDA S 1 1 1 0 1 A1 A0 1 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 A 7 6 5 4 3 2 1 0 1 P
R/W Acknowledge
From Slave
Acknowledge
From Master
Acknowledge
From Master
Acknowledge
From Master
No Acknowledge
From Master
Read From Port 0
Data Into Port 0
Read From Port 1
Data Into Port 1
INT
tiv
tir
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 31 for these details).
Figure 32. Read Input Port Register, Scenario 1
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SCL
123456789
10.x
SDA S 1 1 1 0 1 A1 A0 1 A
00
Acknowledge
R/W From Slave
tph
Read From Port 0
Data Into Port 0
Read From Port 1
Data 00
Data 01
Data Into Port 1
Data 10
11.x
A
10
Acknowledge
From Master
Data 02
tph
Data 11
10.x
A
03
Acknowledge
From Master
tps
Data 03
11.x
A
12
Acknowledge
From Master
1P
No Acknowledge
From Master
tps
Data 12
INT
tiv
tir
A. Transfer of data can be stopped at any time by a Stop condition. When this occurs, data present at the latest
acknowledge phase is valid (output mode). It is assumed that the command byte previously has been set to 00 (Read
Input Port register).
B. This figure eliminates the command byte transfer, a restart, and slave address call between the initial slave address
call and actual data transfer from the P port (see Figure 31 for these details).
Figure 33. Read Input Port Register, Scenario 2
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