SN74AUP1G126_17 Datasheet, PDF (3/40 Pages) Texas Instruments – Low-Power Single Bus Buffer Gate With 3-State Output

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5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
OE
1
5
V
CC
A
2
GND
3
4
Y
SN74AUP1G126
SCES596G – JULY 2004 – REVISED AUGUST 2017
DKC Package
5-Pin SOT-23
Top View
OE
1
5V
CC
A
2
GND
3
4Y
DRL Package
5-Pin SOT-5X3
Top View
OE 1
A2
GND 3
5
V
CC
4Y
DPW Package⁽¹⁾
5-Pin X2SON
Top View
OE
GND
V_CC
A
Y
(1) Preview only
DRY Package
6-Pin SON
Top View
OE ¹
A²
GND ³
6V
CC
5 N.C.
4Y
N.C. – No internal connection.
See mechanical drawings for dimensions.
YFP Package
6-Pin DSBGA
Bottom View
1
2
C _{GND Y}
B
A DNU
A
OE
VCC
Not to scale
DSF Package
6-Pin SON
Top View
OE ¹
A²
6V
CC
5 _N.C.
GND ³
4_Y
YZP Package
5-Pin DSBGA
Bottom View
1
2
C _GND
Y
B
A
A
OE
VCC
Not to scale
PIN
NAME
DBV, DCK, DRY,
DRL, DPW DSF
YFP
A
2
2
B1
DNU
—
—
—
GND
3
3
C1
N.C.
—
5
B2
OE
1
1
A1
V_CC
5
6
A2
Y
4
4
C2
Pin Functions
I/O
YZP
DESCRIPTION
B1
I
Input
B2
— Do not use
C1
— Ground
—
— No Internal Connection
A1
I
Output enable (active high)
A2
— Positive supply
C2
O Buffered output
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