SN74AUP1G126_17 Datasheet, PDF (14/40 Pages) Texas Instruments – Low-Power Single Bus Buffer Gate With 3-State Output

SN74AUP1G126
SCES596G – JULY 2004 – REVISED AUGUST 2017
8 Detailed Description
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8.1 Overview
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable
applications. This family of devices is specified for low static and dynamic power consumption across the entire
V_CC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal
integrity (see Figure 7 and Figure 8).
The SN74AUP1G126 device contains one buffer gate device with output enable control and performs the
Boolean function Y = A. This device is fully specified for partial-power-down applications using I_off . The I_off
circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device
which prevents damage to the device.
To assure the high-impedance state during power up or power down, OE must be tied to GND through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
8.2 Functional Block Diagram
1
OE
2
A
Figure 4. Logic Diagram (Positive Logic)
4
Y
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device
creates fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the power output of the device to be limited to avoid thermal runaway and
damage due to over-current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must
be followed at all times.
8.3.2 Standard CMOS Inputs
Standard CMOS inputs are high impedance and are typically modelled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
Signals applied to the inputs must have fast edge rates, as defined by Δt/Δv in Recommended Operating
Conditions to avoid excessive currents and oscillations. If a slow or noisy input signal is required, a device with a
Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.
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