SN74AUP1G126_17 Datasheet, PDF (16/40 Pages) Texas Instruments – Low-Power Single Bus Buffer Gate With 3-State Output

SN74AUP1G126
SCES596G – JULY 2004 – REVISED AUGUST 2017
9 Application and Implementation
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NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74AUP1G126 device is an output enabled CMOS buffer that can be used in LED indicator applications
that require less than 4 mA. The device can produce up to 4 mA of drive current at 3.3 V. The inputs to the
device are also overvoltage tolerant up to 3.6 V, allowing it to translate down to any valid V_CC.
9.2 Typical Application
Override
MCU Input
V_CC
OE
V_CC
LED
A
Y
Indicator
Output
Figure 6. Application Schematic with MCU driving an LED Indicator
9.2.1 Design Requirements
This device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it
can drive currents that would exceed maximum limits. The output drive strength of this device creates fast edges
into light loads so routing and load conditions should be considered to prevent ringing.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions
– Rise time and fall time specs. See (Δt/ΔV) in the Recommended Operating Conditions table.
– Specified high and low levels. See (V_IH and V_IL) in the Recommended Operating Conditions table.
– Inputs are overvoltage tolerant allowing them to go as high as (V_I max) in the Recommended Operating
Conditions table at any valid V_CC.
2. Recommended Output Conditions
– Load currents should not exceed (I_O max) per output and should not exceed (Continuous current through
V_CC or GND) total current for the part. These limits are located in the Absolute Maximum Ratings table.
– Outputs should not be pulled above V_CC.
9.2.3 Application Curves
3.3-V
Logic⁽¹⁾
3.3-V
Logic⁽¹⁾
(1)
Single, dual, and triple gates
Figure 7. AUP – The Lowest-Power Family
3.5
3
2.5
2
1.5
1
.5
0
-0.5
0
Input
Output
5 10 15 20 25 30 35 40 45
Time - ns
(1) _{AUP1G08 data at CL = 15 pF}
Figure 8. Excellent Signal Integrity
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