SN74AUP1G126_17 Datasheet, PDF (13/40 Pages) Texas Instruments – Low-Power Single Bus Buffer Gate With 3-State Output

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7.2 (Enable and Disable Times)
From Output
Under Test
CL
(See Note A)
SN74AUP1G126
SCES596G – JULY 2004 – REVISED AUGUST 2017
5k
5k
S1
2 X VCC
GND
Load Circut
Test
tPLZ / tPZL
tPHZ / tPZH
S1
2 x VCC
GND
VCC = 0.8 V
VCC = 1.2 V
± 0.1 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
CL
VM
VI
Vû
5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF 5, 10, 15, 30 pF
VCC / 2
VCC
VCC / 2
VCC
VCC / 2
VCC
VCC / 2
VCC
VCC / 2
VCC
VCC / 2
VCC
Output
Control
VCC / 2
Vcc
VCC / 2
0V
Output Waveform 1
tPZL
S1 at 2 x VCC
(See Note B)
tPZH
Output Waveform
2 S1 at GND
(See Note B)
VCC / 2
VCC / 2
tPLZ
VOL + Vû
tPHZ
VOH - V_û
Vcc
VOL
VOH
§0V
Voltage Waveforms Propagation Delay
Times Inverting and Noninverting Outputs
Notes: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such tht the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: 355 ” 10 MHz, ZO= 50 , tr / tf = 3 ns
D. The outputs are measured one at a time, with one transmision per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
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