TMS320DM8148_1109 Datasheet, PDF (296/360 Pages) Texas Instruments – TMS320DM814x DaVinci Digital Media Processors

TMS320DM8148, TMS320DM8147, TMS320DM8146
SPRS647B – MARCH 2011 – REVISED SEPTEMBER 2011
www.ti.com
Table 8-68. Bulk Bypass Capacitors
NO.
PARAMETER
1 DDR_1V5 bulk bypass capacitor count⁽¹⁾
MIN
MAX UNIT
6
Devices
2 DDR_1V5 bulk bypass total capacitance
140
μF
(1) These devices should be placed near the devices they are bypassing, but preference should be given to the placement of the
high-speed (HS) bypass capacitors and DDR3 signal routing.
8.13.1.2.9 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critcal for proper DDR3 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. Table 8-69 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB. Generally speaking, it is good to:
1. Fit as many HS bypass capacitors as possible.
2. Minimize the distance from the bypass cap to the pins/balls being bypassed.
3. Use the smallest physical sized capacitors possible with the highest capacitance readily available.
4. Connect the bypass capacitor pads to their vias using the widest traces possible and using the largest
hole size via possible.
5. Minimize via sharing. Note the limites on via sharing shown in Table 8-69.
Table 8-69. High-Speed Bypass Capacitors
NO.
PARAMETER
1 HS bypass capacitor package size⁽¹⁾
2 Distance, HS bypass capacitor to processor being bypassed^(2)(3)(4)
MIN
TYP
MAX UNIT
201
402 10 Mils
400 Mils
3 Processor DDR_1V5 HS bypass capacitor count
70
Devices
4 Processor DDR_1V5 HS bypass capacitor total capacitance
5 Number of connection vias for each device power/ground ball⁽⁵⁾
6 Trace length from device power/ground ball to connection via⁽²⁾
7 Distance, HS bypass capacitor to DDR device being bypassed⁽⁶⁾
8 DDR3 device HS bypass capacitor count⁽⁷⁾
9 DDR3 device HS bypass capacitor total capacitance⁽⁷⁾
10 Number of connection vias for each HS capacitor⁽⁸⁾⁽⁹⁾
11 Trace length from bypass capacitor connect to connection via⁽²⁾⁽⁹⁾
12 Number of connection vias for each DDR3 device power/ground ball⁽¹⁰⁾
13 Trace length from DDR3 device power/ground ball to connection via⁽²⁾⁽⁸⁾
5
μF
Vias
35
70 Mils
150 Mils
12
Devices
0.85
μF
2
Vias
35
100 Mils
1
Vias
35
60 Mils
(1) LxW, 10-mil units, i.e., a 0402 is a 40x20-mil surface-mount capacitor.
(2) Closer/shorter is better.
(3) Measured from the nearest processor power/ground ball to the center of the capacitor package.
(4) Three of these capacitors should be located underneath the processor, between the cluster of DDR_1V5 balls and ground balls,
between the DDR interfaces on the package.
(5) See the Via Channel™ escape for the processor package.
(6) Measured from the DDR3 device power/ground ball to the center of the capacitor package.
(7) Per DDR3 device.
(8) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board. No sharing of
vias is permitted on the same side of the board.
(9) An HS bypass capacitor may share a via with a DDR device mounted on the same side of the PCB. A wide trace should be used for the
connection and the length from the capacitor pad to the DDR device pad should be less than 150 mils.
(10) Up to a total of two pairs of DDR power/ground balls may share a via.
8.13.1.2.9.1 Return Current Bypass Capacitors
Use additional bypass capacitors if the return current reference plane changes due to DDR3 signals
hopping from one signal layer to another. The bypass capacitor here provides a path for the return current
to hop planes along with the signal. As many of these return current bypass capacitors should be used as
possible. Since these are returns for signal current, the signal via size may be used for these capacitors.
296 Peripheral Information and Timings
Copyright © 2011, Texas Instruments Incorporated
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