TMS320DM8148_1109 Datasheet, PDF (286/360 Pages) Texas Instruments – TMS320DM814x DaVinci Digital Media Processors

TMS320DM8148, TMS320DM8147, TMS320DM8146
SPRS647B – MARCH 2011 – REVISED SEPTEMBER 2011
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8.13.1.1.2.7 High-Speed Bypass Capacitors
High-speed (HS) bypass capacitors are critical for proper DDR2 interface operation. It is particularly
important to minimize the parasitic series inductance of the HS bypass capacitors, processor/DDR power,
and processor/DDR ground connections. Table 8-55 contains the specification for the HS bypass
capacitors as well as for the power connections on the PCB.
Table 8-55. High-Speed Bypass Capacitors
NO.
PARAMETER
1 HS bypass capacitor package size⁽¹⁾
MIN
MAX UNIT
0402 10 Mils
2 Distance from HS bypass capacitor to device being bypassed
3 Number of connection vias for each HS bypass capacitor⁽²⁾
250 Mils
2
Vias
4 Trace length from bypass capacitor contact to connection via
1
30 Mils
5 Number of connection vias for each processor power/ground ball
1
Vias
6 Trace length from processor power/ground ball to connection via
35 Mils
7 Number of connection vias for each DDR2 device power/ground ball
1
Vias
8 Trace length from DDR2 device power/ground ball to connection via
9 DVDD18 HS bypass capacitor count⁽³⁾⁽⁴⁾
10 DVDD18 HS bypass capacitor total capacitance⁽⁵⁾
11 DDR device HS bypass capacitor count⁽⁶⁾⁽⁷⁾
12 DDR device HS bypass capacitor total capacitance⁽⁷⁾
35 Mils
40
Devices
2.4
μF
8
Devices
0.4
μF
(1) LxW, 10-mil units, i.e., a 0402 is a 40x20-mil surface-mount capacitor.
(2) An additional HS bypass capacitor can share the connection vias only if it is mounted on the opposite side of the board.
(3) These devices should be placed as close as possible to the device being bypassed.
(4) Use half of these capacitors for DDR[0] and half for DDR[1].
(5) Use half of these capacitors for DDR[0] and half for DDR[1].
(6) These devices should be placed as close as possible to the device being bypassed.
(7) Per DDR device.
8.13.1.1.2.8 Net Classes
Table 8-56 lists the clock net classes for the DDR2 interface. Table 8-57 lists the signal net classes, and
associated clock net classes, for the signals in the DDR2 interface. These net classes are used for the
termination and routing rules that follow.
Table 8-56. Clock Net Class Definitions
CLOCK NET CLASS PROCESSOR PIN NAMES
CK
DDR[x]_CLK/DDR[x]_CLK
DQS0
DDR[x]_DQS[0]/DDR[x]_DQS[0]
DQS1
DQS2 ⁽¹⁾
DQS3 ⁽¹⁾
DDR[x]_DQS[1]/DDR[x]_DQS[1]
DDR[x]_DQS[2]/DDR[x]_DQS[2]
DDR[x]_DQS[3]/DDR[x]_DQS[3]
(1) Only used on 32-bit wide DDR2 memory systems.
286 Peripheral Information and Timings
Copyright © 2011, Texas Instruments Incorporated
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