TMS320DM8148_1109 Datasheet, PDF (279/360 Pages) Texas Instruments – TMS320DM814x DaVinci Digital Media Processors

TMS320DM8148, TMS320DM8147, TMS320DM8146
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SPRS647B – MARCH 2011 – REVISED SEPTEMBER 2011
specification. The design rules constrain PCB trace length, PCB trace skew, signal integrity, cross-talk,
and signal timing. These rules, when followed, result in a reliable DDR2 memory system without the need
for a complex timing closure process. For more information regarding the guidelines for using this DDR2
specification, see the Understanding TI’s PCB Routing Rule-Based DDR Timing Specification Application
Report (Literature Number: SPRAAV0).
8.13.1.1.2.1 DDR2 Interface Schematic
Figure 8-48 shows the DDR2 interface schematic for a x32 DDR2 memory system. In Figure 8-49 the x16
DDR2 system schematic is identical except that the high-word DDR2 device is deleted.
Copyright © 2011, Texas Instruments Incorporated
Peripheral Information and Timings 279
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