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| TMS320DM8148_1109 Datasheet, PDF (202/360 Pages) Texas Instruments – TMS320DM814x DaVinci Digital Media Processors | |||
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TMS320DM8148, TMS320DM8147, TMS320DM8146
SPRS647B â MARCH 2011 â REVISED SEPTEMBER 2011
www.ti.com
Table 7-16. Timing Requirements for AUX_MXI/AUX_CLKIN (1) (2) (see Figure 7-13)
OPP100
NO.
MIN
NOM
1 tc(AMXI)
Cycle time, AUXOSC_MXI/AUX_CLKIN
33.3
50
2 tw(AMXIH)
Pulse duration, AUXOSC_MXI/AUX_CLKIN high
0.45C
3 tw(AMXIL)
Pulse duration, AUXOSC_MXI/AUX_CLKIN low
0.45C
4 tt(AMXI)
Transition time, AUXOSC_MXI/AUX_CLKIN
5 tJ(AMXI)
6 Sf
Period jitter, AUXOSC_MXI/AUX_CLKIN
Frequency stability, AUXOSC_MXI/AUX_CLKIN(3)
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) C = AUX_CLKIN cycle time in ns. For example, when AUXOSC_MXI/AUX_CLKIN frequency is 20 MHz, use C = 50 ns.
(3) Applies only when sourcing the HDMI or HDVPSS DAC clocks from the AUXOSC.
UNIT
MAX
50 ns
0.55C ns
0.55C ns
7 ns
0.02C ns
± 50 ppm
AUXOSC_MXI/
AUX_CLKIN
5
1
1
4
2
3
4
Figure 7-13. AUX_MXI/AUX_CLKIN Timing
202 Power, Reset, Clocking, and Interrupts
Copyright © 2011, Texas Instruments Incorporated
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Product Folder Link(s): TMS320DM8148 TMS320DM8147 TMS320DM8146
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