THS10082_09 Datasheet, PDF (28/37 Pages) Texas Instruments – 10-BIT, TWO ANALOG INPUT, 8-MSPS, SIMULTANAEOUS SAMPLING

THS10082
SLAS254B − MAY 2002 − REVISED NOVEMBER 2002
www.ti.com
Read Timing Parameter (CS0-Controlled)⁽¹⁾
PARAMETER
tsu(R/W) Setup time, R/W high to last CS valid
ta
Access time, last CS valid to data valid
td(CSDAV) Delay time, last CS valid to DATA_AV inactive
th
Hold time, first CS invalid to data invalid
th(R/W)
Hold time, first external CS invalid to R/W change
tw(CS)
Pulse duration, CS active
(1) _{CS = CS0}
MIN TYP MAX UNIT
0
ns
0
10 ns
12
ns
0
5 ns
5
ns
10
ns
Write Timing (Using R/W, CS0-Controlled)
Figure 37 shows the write-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W.
The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last
external signal of CS0, CS1, and R/W which becomes valid.
tw(CS)
CS0
10%
10%
90%
CS1
WR^{ÓÓÓÓÓÓÓÓÓ}
RD
D(0−9)
tsu(R/W)
90%
th(R/W)
tsu
ÓÓÓÓÓÓÓÓÓ
th
90%
DATA_AVÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖÖ
Figure 37. Write Timing Diagram Using R/W (CS0-controlled)
Write Timing Parameter (CS0-Controlled)⁽¹⁾
PARAMETER
tsu(R/W) Setup time, R/W stable to last CS valid
tsu
Setup time, data valid to first CS invalid
th
Hold time, first CS invalid to data invalid
th(R/W)
Hold time, first CS invalid to R/W change
tw(CS)
Pulse duration, CS active
(1) _{CS = CS0}
MIN TYP MAX UNIT
0
ns
5
ns
2
ns
5
ns
10
ns
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