THS10082_09 Datasheet, PDF (15/37 Pages) Texas Instruments – 10-BIT, TWO ANALOG INPUT, 8-MSPS, SIMULTANAEOUS SAMPLING

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THS10082
SLAS254B − MAY 2002 − REVISED NOVEMBER 2002
DETAILED DESCRIPTION
Reference Voltage
The THS10082 has a built-in reference, which provides the reference voltages for the ADC. VREFP is set to 3.5 V and
VREFM is set to 1.5 V. An external reference can also be used through two reference input pins, REFP and REFM, if the
reference source is programmed as external. The voltage levels applied to these pins establish the upper and lower limits
of the analog inputs to produce a full-scale and zero-scale reading respectively.
Analog Inputs
The THS10082 consists of two analog inputs, which are sampled simultaneously. These inputs can be selected individually
and configured as single-ended or differential inputs. The desired analog input channel can be programmed.
Analog-to-Digital Converter
The THS10082 uses a 10-bit pipelined multistaged architecture with four 1-bit stages followed by four 2-bit stages, which
achieves a high sample rate with low power consumption. The THS10082 distributes the conversion over several smaller
ADC sub-blocks, refining the conversion with progressively higher accuracy as the device passes the results from stage
to stage. This distributed conversion requires a small fraction of the number of comparators used in a traditional flash ADC.
A sample-and-hold amplifier (SHA) within each of the stages permits the first stage to operate on a new input sample while
the second through the eighth stages operate on the seven preceding samples.
DATA_AV
In continuous conversion mode, the first DATA_AV signal is delayed by (7+TL) cycles of the CONV_CLK after a FIFO reset.
This is due to the latency of the pipeline architecture of the THS10082.
Conversion Modes
The conversion can be performed in two different conversion modes. In the single conversion mode, the conversion is
initiated by an external signal (CONVST). An internal oscillator controls the conversion time. In the continuous conversion
mode, an external clock signal is applied to the clock input (CONV_CLK). A new conversion is started with every falling
edge of the applied clock signal.
Sampling Rate
The maximum possible conversion rate per channel is dependent on the selected analog input channels. Table 1 shows
the maximum conversion rate in the continuous conversion mode for different combinations.
Table 1. Maximum Conversion Rate in Continuous Conversion Mode
CHANNEL CONFIGURATION
One single-ended channel
Two single-ended channels
One differential channel
NUMBER OF
CHANNELS
1
2
1
MAXIMUM CONVERSION
RATE PER CHANNEL
8 MSPS
4 MSPS
8 MSPS
The maximum conversion rate in the continuous conversion mode per channel, fc, is given by:
fc
+
8 MSPS
# channels
Table 2 shows the maximum conversion rate in the single conversion mode.
Table 2. Maximum Conversion Rate in Single Conversion Mode⁽¹⁾
CHANNEL CONFIGURATION
1 single-ended channel
2 single-ended channels
1 differential channel
NUMBER OF
CHANNELS
1
2
1
MAXIMUM CONVERSION
RATE PER CHANNEL
4 MSPS
2.67 MSPS
4 MSPS
(1) _{The maximum conversion rate with respect to the typical internal oscillator speed [i.e., 8 MHz × (tc/t2)].}
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