THS10082_09 Datasheet, PDF (24/37 Pages) Texas Instruments – 10-BIT, TWO ANALOG INPUT, 8-MSPS, SIMULTANAEOUS SAMPLING

THS10082
SLAS254B − MAY 2002 − REVISED NOVEMBER 2002
www.ti.com
ANALOG INPUT CHANNEL SELECTION
The analog input channels of the THS10082 can be selected via bits 3 to 7 of control register 0. One single channel
(single-ended or differential) is selected via bit 3 of control register 0. Bit 5 controls the selection between single-ended and
differential configuration. Bit 6 selects the autoscan mode, if more than one input channel is selected. Table 10 shows the
possible selections.
Table 10. Analog Input Channel Configurations
BIT 7
SCAN
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
BIT 6
DIFF1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
1
1
1
1
BIT 5
DIFF0
0
0
0
0
1
1
0
0
0
1
1
0
1
1
0
1
1
0
0
0
1
1
1
1
BIT 4
CHSEL1
0
0
1
1
0
0
0
1
1
0
1
0
1
1
0
0
1
0
1
1
0
0
1
1
BIT 3
CHSEL0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
0
1
DESCRIPTION OF THE SELECTED INPUTS
Analog input AINP (single ended)
Analog input AINM (single ended)
Reserved
Reserved
Differential channel (AINP−AINM)
Reserved
Autoscan two single-ended channels: AINP, AINM, AINP, …
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Test Mode
The test mode of the ADC is selected via bit 8 and bit 9 of control register 0. The different selections are shown in Table 11.
Table 11. Test Mode
BIT 9
TEST1
0
0
1
1
BIT 8
TEST0
0
1
0
1
OUTPUT RESULT
Normal mode
VREFP
((VREFM)+(VREFP))/2
VREFM
Three different options can be selected. This feature allows support testing of hardware connections between the ADC and
the processor.
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