THS10082_09 Datasheet, PDF (27/37 Pages) Texas Instruments – 10-BIT, TWO ANALOG INPUT, 8-MSPS, SIMULTANAEOUS SAMPLING

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THS10082
SLAS254B − MAY 2002 − REVISED NOVEMBER 2002
DATA_AV Type
Bit 4 and bit 5 (DATA_T, DATA_P) of control register 1 are used to program the signal DATA_AV. Bit 4 of control register 1
determines whether the DATA_AV signal is static or a pulse. Bit 5 of the control register determines the polarity of
DATA_AV. This is shown in Table 14.
Table 14. DATA_AV Type
BIT 5
DATA_P
0
0
1
1
BIT 4
DATA_T
0
1
0
1
DATA_AV TYPE
Active low level
Active low pulse
Active high level
Active high pulse
The signal DATA_AV is set to active when the trigger condition is satisfied. It is set back inactive dependent of the DATA_T
selection (pulse or level).
If level mode is chosen, DATA_AV is set inactive after the first of the TL (TL = trigger level) reads (with the falling edge of
READ). The trigger condition is checked again after TL reads. For single conversion mode, the DATA_AV type should be
programmed to active level mode.
If pulse mode is chosen, the signal DATA_AV is a pulse with a width of one half of a CONV_CLK cycle in continuous
conversion mode.
Read Timing (Using R/W, CS0-Controlled)
Figure 36 shows the read-timing behavior when the WR(R/W) input is programmed as a combined read-write input R/W.
The RD input has to be tied to high-level in this configuration. This timing is called CS0-controlled because CS0 is the last
external signal of CS0, CS1, and R/W which becomes valid.
tw(CS)
CS0
10%
10%
90%
CS1
R/W ^{ÓÓÓÓÓÓÓÓÓ90%}
RD
D(0−9)
DATA_AV
tsu(R/W)
ta
90%
td(CSDAV)
90%
ÔÔÔÔÔÔÔÔÔ ^th(R/W)
90%
th
90%
Figure 36. Read Timing Diagram Using R/W (CS0-controlled)
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