ADS1291_14 Datasheet, PDF (27/75 Pages) Texas Instruments – Power, 2-Channel, 24-Bit Analog Front-End for Biopotential Measurements

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ADS1291
ADS1292
ADS1292R
SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012
CLOCK
The ADS1291, ADS1292, and ADS1292R provide two different methods for device clocking: internal and
external. Internal clocking is ideally suited for low-power, battery-powered systems. The internal oscillator is
trimmed for accuracy at room temperature. Over the specified temperature range the accuracy varies; see the
Electrical Characteristics. Clock selection is controlled by the CLKSEL pin and the CLK_EN register bit.
The CLKSEL pin selects either the internal or external clock. The CLK_EN bit in the CONFIG2 register enables
and disables the oscillator clock to be output in the CLK pin. A truth table for these two pins is shown in Table 9.
The CLK_EN bit is useful when multiple devices are used in a daisy-chain configuration. It is recommended that
during power-down the external clock be shut down to save power.
CLKSEL PIN
0
1
1
Table 9. CLKSEL Pin and CLK_EN Bit
CONFIG2.CLK_EN
BIT
X
0
1
CLOCK SOURCE
External clock
Internal clock oscillator
Internal clock oscillator
CLK PIN STATUS
Input: external clock
3-state
Output: internal clock oscillator
The ADS1291, ADS1292, and ADS1292R have the option to choose between two different external clock
frequencies (512 kHz or 2.048 MHz). This frequency is selected by setting the CLK_DIV bit (bit 6) in the
LOFF_STAT register. The modulator must be clocked at 128 kHz, regardless of the external clock frequency.
Figure 33 shows the relationship between the external clock (f_CLK) and the modulator clock (f_MOD). The default
mode of operation is f_CLK = 512 kHz. The higher frequency option has been provided to allow the SPI to run at a
higher speed. SCLK can be only twice the speed of f_CLK during a register read or write, see section on sending
multi-byte commands. Having the 2.048 MHz option allows for register read and writes to be performed at SCLK
speeds up to 4.096 MHz.
f_CLK
Frequency
Divider
Divide-By-4
Frequency
Divider
Divide-By-16
f_MOD
CLK_DIV
(Bit 6 of LOFF_STAT
Register)
Figure 33. Relationship Between External Clock (f_CLK) and Modulator Clock (f_MOD)
Copyright © 2011–2012, Texas Instruments Incorporated
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