ADS1291_14 Datasheet, PDF (10/75 Pages) Texas Instruments – Power, 2-Channel, 24-Bit Analog Front-End for Biopotential Measurements

ADS1291
ADS1292
ADS1292R
SBAS502B – DECEMBER 2011 – REVISED SEPTEMBER 2012
www.ti.com
TIMING CHARACTERISTICS
t_CLK
CLK
t_CSSC
CS
t_SDECODE
t_CSH
SCLK
t_SCLK
t_SPWH
t_SPWL
t_SCCS
1
2
3
8
1
2
3
8
DIN
Hi-Z
DOUT
t_DIST
t_CSDOD
t_DIHD
t_DOPD
t_CSDOZ
Hi-Z
NOTE: SPI settings are CPOL = 0 and CPHA = 1.
Figure 1. Serial Interface Timing
Timing Requirements For Figure 1⁽¹⁾
2.7 V ≤ DVDD ≤ 3.6 V
PARAMETER
DESCRIPTION
MIN TYP MAX
Master clock period (CLK_DIV bit of LOFF_STAT register = 0) 1775
2170
t_CLK
Master clock period (CLK_DIV bit of LOFF_STAT register = 1)
444
542
t_CSSC
t_SCLK
t_{SPWH, L}
t_DIST
t_DIHD
t_DOPD
t_CSH
t_CSDOD
t_SCCS
t_SDECODE
t_CSDOZ
CS low to first SCLK, setup time
SCLK period
SCLK pulse width, high and low
DIN valid to SCLK falling edge: setup time
Valid DIN after SCLK falling edge: hold time
SCLK rising edge to DOUT valid
CS high pulse
CS low to DOUT driven
Eighth SCLK falling edge to CS high
Command decode time
CS high to DOUT Hi-Z
6
50
15
10
10
12
2
10
3
4
10
(1) Specifications apply from –40°C to +85°C. Load on D_OUT = 20 pF || 100 kΩ.
1.7 V ≤ DVDD ≤ 2 V
MIN TYP MAX
1775
2170
444
542
17
66.6
25
10
11
22
2
20
3
4
20
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
t_CLKs
ns
t_CLKs
t_CLKs
ns
10
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