LMH6586_14 Datasheet, PDF (25/34 Pages) Texas Instruments – 32x16 Video Crosspoint Switch

LMH6586
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SNCS105D – JULY 2008 – REVISED MARCH 2013
READ SEQUENCE
Read sequences are comprised of two I²C transfers shown. The first is the address access transfer, which
consists of a write sequence that transfers only the address to be accessed. The second is the data read
transfer, which starts at the address accessed in the first transfer and increments to the next address per data
byte read until a stop condition is encountered.
The address access transfer consists of a start condition, the slave device address including the read/write bit (a
zero, indicating a write), and the ACK bit. The next byte is the address to be accessed, followed by the ACK bit
and the stop condition to indicate the end of the address access transfer.
The subsequent read data transfer consists of a start condition, the slave device address including the read/write
bit (a one, indicating a read), and the ACK bit. The next byte is the data read from the initial access address.
Subsequent read data bytes will correspond to the next increment address locations. Note that each data byte is
followed by an ACK bit until a stop condition is encountered, indicating the end of the sequence.
The timing diagram for the read sequence is shown in Figure 55, which uses the 7-bit slave address from the
previous examples.
SCL
SDA
Start
Condition
A7 A6 A5 A4 A3 A2 A1 A0
000000100
0
Write Address Byte (0 x 02)
Address
Acknowledge
SCL
SDA
Start
Condition
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0 00 0 0 0 1 1 0
0
0
Read Address Byte (0 x 03)
Data Byte 1
Acknowledge
Data Byte n
Stop
Condition
Figure 55. LMH6586 Read Sequence
REGISTER DESCRIPTIONS
Video and Sync Detection Status Registers
Registers 0x00 to 0x03 (read-only) contain the sync detection status bits for all 32 input channels. Any input (m)
has a sync detection status bit (SD_m) that can flag high when a loss of sync is detected; otherwise, the status
bit will be low to indicate presence of sync.
Registers 0x04 to 0x07 (read-only) contain the video detection status bits for all 32 input channels. Any input (m)
has a video detection status bit (VD_m) that can flag high when either loss of video or presence of video is
detected, depending on the respective invert control bit (see Video Detection Invert Registers). Assuming the
default setting for the invert control bit, the status bit (VD_m) will flag high when loss of video is detected on the
input; otherwise, the status bit will be low indicating presence of video.
Video and Sync Detection Control Registers
Video Detection Invert Registers
Registers 0x0C to 0x0F contain the video detection invert control bits for all input channels. Any input (m) has a
invert control bit that can invert the polarity of the video detection status bit (VD_INV_m). When the invert bit
(VD_INV_m) is set to 0 (default), the respective status bit (VD_m) will flag high to indicate loss of video on the
input; otherwise, when the invert bit is set to 1, the status bit will flag high to indicate presence of video.
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