LMH6586_14 Datasheet, PDF (18/34 Pages) Texas Instruments – 32x16 Video Crosspoint Switch

LMH6586
SNCS105D – JULY 2008 – REVISED MARCH 2013
APPLICATION INFORMATION
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FUNCTIONAL OVERVIEW
The LMH6586 is a non-blocking, analog video crosspoint switch with 32 input channels and 16 output channels.
The inputs have integrated DC restore clamp circuits for biasing the AC-coupled video inputs. The fully buffered
outputs have selectable gain and can drive one back-terminated video load (150Ω). The LMH6586 includes an
extra output (VOUT_16) with 1X fixed gain that can be used to feed any input's video signal to an external video
sync separator, such as the LMH1980 or LMH1981.
Each input and each output can be individually placed in shutdown mode by programming the input shutdown
and output shutdown registers, respectively. Additionally, the PWDN pin (pin 70) can be set high to enable Power
Down mode, which shuts down all input and output video channels while preserving all register settings.
The LMH6586 also features both video detection and sync detection functions on each input channel. Additional
flexibility is provided by user-defined threshold levels for both video and sync detection features. The status of
both detection schemes can be read from the video and sync detection status registers. Additionally, the FLAG
output (pin 75) can be used to indicate if video detection or sync detection is triggered on any combination of
input channels and detection types enabled by the user.
OUTPUT BUFFER GAIN
The LMH6586 has an output buffer with a selectable gain of 1X or 2X. When the GAIN_SEL input (pin 61) is set
low, output channels 0–15 will have a gain of 1X. When it is set high, they will have a gain of 2X. Regardless of
the gain select setting, output channel 16 has 1X fixed gain since the output is intended to drive an optional
external sync separator through a 0.1 µF capacitor and no load termination.
VIDEO DETECTION
This type of detection can be configured to indicate when an input's video signal is detected above the threshold
level (“presence of video” ) or below the threshold level (“loss of video”). The video threshold voltage level is
common to all 32 input channels and is selectable by programming register 0x1D. As shown in Table 1, the three
LSBs (bits 2:0) of this register can be used to set the threshold level in 95 mV steps (typical) above to the sync
tip level of the DC-restored input. Additionally, to prevent undesired triggering on high-frequency picture content,
such as on-screen display (OSD) or text, the detection circuit actually analyzes a low-pass-filtered version of the
video signal. The first-order RC filter is included on-chip and has a corner frequency of about 1 kHz.
Registers 0x04 to 0x07 (read-only) contain the video detection status bits for all 32 input channels. Any input (m)
has a video detection status bit (VD_m) that can flag high when either loss of video or presence of video is
detected, depending on the respective invert control bit. Registers 0x0C to 0x0F contain the video detection
invert control bits for all input channels. When the invert bit (VD_INV_m) is set to 0 (default setting), the
respective status bit (VD_m) will flag high when loss of video is detected on the input; otherwise, when the invert
bit is set to 1, the status bit will flag high when presence of video is detected.
Table 1. Video Detect Threshold Voltage⁽¹⁾
Register
0x1D [2:0]
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Threshold level above the
sync tip level
491 mV
587 mV
683 mV
778 mV
873 mV
968 mV
1062 mV
1156 mV
(1) See Video Detect parameters in Electrical Characteristics
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