LMH6586_14 Datasheet, PDF (24/34 Pages) Texas Instruments – 32x16 Video Crosspoint Switch

LMH6586
SNCS105D – JULY 2008 – REVISED MARCH 2013
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ADDR[1]
(pin 72)
0
0
1
1
Table 2. I²C Device Slave Address Lookup Table
ADDR[0]
(pin 71)
7-bit I²C Slave Address (binary)
0
0000 000x
1
0000 001x
0
0000 010x
1
0000 011x
For example, if ADDR[1] is set low and ADDR[0] is set high, then the 7-bit slave address would be “0000 001” in
binary. Therefore, the address byte for write sequences is 0x02 (“0000 0010”) and the address byte read
sequences is 0x03 (“0000 0011”). Figure 54 and Figure 55 show write and read sequences across the I²C
interface.
WRITE SEQUENCE
The write sequence begins with a start condition, which consists of the master pulling SDA low while SCL is held
high. The slave device address is sent next. The address byte is made up of an address of seven bits (7:1) and
the read/write bit (0). Bit 0 is low to indicate a write operation. Each byte that is sent is followed by an
acknowledge (ACK) bit. When SCL is high the master will release the SDA line. The slave must pull SDA low to
acknowledge. The address of the register to be written to is sent next. Following the register address and the
ACK bit, the data byte for the register is sent. When more than one data byte is sent, the register pointer is
automatically incremented to write to the next address location. Note that each data byte is followed by an ACK
bit until a stop condition is encountered, indicating the end of the sequence.
The timing diagram for the write sequence is shown in Figure 54, which uses the 7-bit slave device address from
the previous example above.
SCL
SDA
Start
Condition
A7 A6 A5 A4 A3 A2 A1 A0
000000100
0
Write Address Byte (0 x 02)
Address
Acknowledge
SCL
SDA
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
Data Byte 1
Data Byte 2
Acknowledge
Data Byte n
Stop
Condition
Figure 54. LMH6586 Write Sequence
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