OMAP5912_16 Datasheet, PDF (248/270 Pages) Texas Instruments – OMAP5912 Applications Processor

Electrical Specifications
5.14 LCD Controller and LCDCONV Interfaces Timing
Table 5−34 assumes testing over recommended operating conditions (see Figure 5−44 and Figure 5−45).
Table 5−34. LCD Controller and LCDCONV Switching Characteristics^†
NO.
PARAMETER
MIN
MAX UNIT
L1 1/[t_c(PCLK)]
L2 t_w(PCLK)
L3 t_r(PCLK)
L4 t_f(PCLK)
Operating frequency, LCD.PCLK
Pulse duration, LCD.PCLK high or low
Rise time, LCD.PCLK
Fall time, LCD.PCLK
0.4P^‡§
20
0.6P^‡§
15
15
MHz
ns
ns
ns
L5 t_d(CLK-VS)
Delay time, LCD.PCLK to LCD.VS transition
−1
1.5 ns
L6 t_d(CLK-HS)
L7 t_d(CLK-PV)
Delay time, LCD.PCLK to LCD.HS transition
Delay time, LCD.PCLK to pixel data
valid (LCD.P[15:0])
LCD 16-bit mode (LCDCONV
bypassed)
LCD 18-bit mode through LCDCONV
(LCD.RED0 and LCD.BLUE0)
−1
1.5 ns
2
ns
7
Delay time, LCD.PCLK to pixel data
LCD 16-bit mode (LCDCONV
bypassed)
−1
L8 t_d(CLK-PIV)
invalid (LCD.P[15:0])
ns
LCD 18-bit mode through LCDCONV
(LCD.RED0 and LCD.BLUE0)
−3.5
L9 t_d(CLK-AC)
Delay time, LCD.PCLK to LCD.AC transition
B − 2^¶
B + 1^¶
ns
† _{Although timing diagrams illustrate the logical function of the TFT mode, static timing applies to all supported modes of operation. Likewise,}
LCD.HS, LCD.VS, and LCD.AC are shown as active-low, but each can optionally be configured as active-high.
‡ _{P = Period of the LCD pixel clock}
§ _{The pixel clock is created in a divider that may also be programmed to divide by odd numbers. In such case, the duty cycle at the output of the}
divider is influenced by the division ratio.
¶ _{B = Period of internal undivided pixel clock}
248 SPRS231E
December 2003 − Revised December 2005