OMAP5912_16 Datasheet, PDF (242/270 Pages) Texas Instruments – OMAP5912 Applications Processor

Electrical Specifications
Table 5−25. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 1)^†‡
MASTER
SLAVE
NO.
UNIT
MIN MAX
MIN MAX
M49 t_su(DRV-CKXH) Setup time, MCBSPx.DR valid before MCBSPx.CLKX high
33.25
0
ns
M50 t_h(CKXH-DRV)
Hold time, MCBSPx.DR valid after MCBSPx.CLKX high
−1
6P + 9
ns
M51 t_su(FXL-CKXL)
Setup time, MCBSPx.FSX low before
MCBSPx.CLKX low
McBSP1
McBSP2
McBSP3
5
5
ns
6
M52 t_c(CKX)
Cycle time, MCBSPx.CLKX
2P
16P
ns
† _{P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.}
Table 5−26. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 1)^†‡
NO.
PARAMETER
MASTER
MIN
MAX
SLAVE
UNIT
MIN
MAX
Hold time, MCBSPx.FSX low after MCBSPx.CLKX
M43 t_{h(CKXH-FXL) high§¶}
C − 10.5 P + 8.25
ns
M44 t_d(FXL-CKXL) Delay time, MCBSPx.FSX low to MCBSPx.CLKX low^§# 2C − 10.5 P + 8.25
ns
M45 t_d(CKXL-DXV) Delay time, MCBSPx.CLKX low to MCBSPx.DX valid
−9.75
10.25 2.75 5P + 34.5 ns
† _{P =1/(DSPPER_CK or DSPXOR_CK) for McBSP1 and McBSP3, or 1/(ARMPER_CK clock frequency) in nanoseconds (ns) for McBSP2.}
‡ _{For all SPI slave modes, CLKG is programmed as 1/2 of the internal reference clock by setting CLKSM = CLKGDV = 1.}
§ _{T = CLKX period = (1 + CLKGDV) * P}
C = CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even.
¶ _{FSRP = FSXP = 1. As a SPI master, MCBSPx.FSX is inverted to provide active-low slave-enable output. As a slave, the active-low signal input}
on MCBSPx.FSX and MCBSPx.FSR is inverted before being used internally.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master McBSP
CLKXM = CLKRM = FSXM = FSRM = 0 for slave McBSP
# _{MCBSPx.FSX must be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master}
clock (MCBSPx.CLKX).
LSB
M51
MSB
M52
MCBSPx.CLKX
M43
M44
MCBSPx.FSX
MCBSPx.DX_or
_DR_(Master)
Bit 0
MCBSPx.DX_or
_DR_(Slave)
Bit 0
Bit (n−1)
M49
Bit (n−1)
M45
Bit (n−2)
Bit (n−3)
Bit (n−2)
M50
Bit (n−3)
Bit (n−4)
Bit (n−4)
Figure 5−38. McBSP Timings as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
242 SPRS231E
December 2003 − Revised December 2005